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* configs: defconfig: Enable APB Timer in agilex5socfpga_agilex5-23.1_RCDinesh Maniyam2023-02-241-0/+2
* arch: arm: dts: Enable APB Timer for agilex5Dinesh Maniyam2023-02-241-0/+16
* arch: arm: dts: Add APB Timer node in SPL Agilex5Dinesh Maniyam2023-02-241-0/+16
* Remove swbld_release2anaraya22023-02-241-7/+0
* pre-idsb enable compilation and simicsDinesh Maniyam2023-02-213-4/+21
* agilex5: agilex5 pre-idsb SimicsManiyam, Dinesh2023-02-2059-78/+5903
* env: fat: Fix warning for unused function get_env_filenameKah Jing Lee2023-01-061-0/+2
* arch: arm: rsu-spl: Compare FACTORY IMAGE with current running SPL slotKah Jing Lee2023-01-061-1/+2
* arch: arm: rsu: Multiboot selection Uboot SSBL for RSU (MMC)Kah Jing Lee2023-01-065-42/+268
* arch: arm: Kconfig: Turn off SOCFPGA_RSU_MULTIBOOT by defaultKah Jing Lee2023-01-061-1/+1
* arch: arm: rsu: Multiboot selection Uboot SSBL for RSURadu Bacrau2023-01-066-1/+224
* arm: socfpga: Add bsp-generator scripts with qts-filterKah Jing Lee2023-01-0610-60/+1986
* HSD #18025336902: intel: n5x: ddr: update license for secure_vabLokanathan, Raaj2023-01-062-4/+4
* HSD #15011830300: ddr: altera: agilex: Update data rate based on HMC rate and...Sin Hui Kho2022-12-162-2/+23
* usb: gadget: dfu: Fix the unchecked length fieldVenkatesh Yadav Abbarapu2022-12-141-21/+37
* HSD #15011972255: drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flashTeik Heng Chong2022-12-091-0/+5
* doc: README.socfpga: Update for U-boot 2022.10Lokanathan, Raaj2022-12-071-5/+5
* arm: configs: Clean up the defconfigs for agilex, stratix10, arria10 and cvLokanathan, Raaj2022-12-078-41/+35
* arm: configs: Set the stack pointer address using CONFIG_CUSTOM_SYS_INIT_SP_ADDRLokanathan, Raaj2022-11-113-0/+6
* HSD #15011820475: arm: dts: soc64: Revert "changing DDR aliasing addresses"Lokanathan, Raaj2022-11-073-66/+6
* configs: socfpga: Add missing CONFIG_SYS_MALLOC_F_LEN into socfpga defconfigLokanathan, Raaj2022-11-012-0/+2
* configs: socfpga: Remove outdated configsLokanathan, Raaj2022-11-012-4/+0
* arm: socfpga: Modify the loader script to support changes from mainline.Lokanathan, Raaj2022-11-011-3/+3
* configs: Remove CONFIG_HW_WATCHDOG from TARGET_SOCFPGA_GEN5Lokanathan, Raaj2022-10-121-1/+0
* drivers: nand: Move the following nand drivers to nand framework objectsLokanathan, Raaj2022-10-121-4/+4
* drivers: fpga: Follow mainline to pass compatible flags to fpga_loadLokanathan, Raaj2022-10-121-1/+2
* configs: soc64: Follow mainline to migrate CONFIG_SYS_BOOTM_LEN to KconfigLokanathan, Raaj2022-10-122-5/+0
* configs: socfpga: Follow mainline to add the following configsLokanathan, Raaj2022-10-1211-0/+120
* jenkins: Enable PR CI/CDBoon Khai Ng2022-10-111-0/+242
* doc: README.socfpga: Update for U-boot 2022.07Lokanathan, Raaj2022-10-111-5/+5
* HSD #15011817806: fs-loader: Doc improvementLokanathan, Raaj2022-10-111-0/+8
* HSD #15011817806: fs-loader: Perform code cleanups on fs-loader driverLokanathan, Raaj2022-10-114-16/+9
* HSD #15011860471: Remove cm_get_qspi_controller_clk_hz from socfpga_soc64_com...Lokanathan, Raaj2022-10-112-13/+0
* HSD #15011858928: configs: Set COUNTER_FREQUENCY configurationsLokanathan, Raaj2022-10-116-0/+6
* HSD #16018042241: arm: dts: arria10: Increase boot partition size for NANDTeoh Ji Sheng2022-10-111-2/+2
* HSD #18019005734: arch: arm: mach-socfpga: SDM Doorbell Issue FixYuslaimi, Alif Zakuan2022-10-111-10/+5
* HSD #14016953396: rsu: ignore fw cpb errors after fixing cpbsRadu Bacrau2022-10-111-2/+6
* HSD #14016896875: rsu: fix cpb headerRadu Bacrau2022-10-111-1/+1
* HSD #18022972407: drivers: clk: Update comment to describe pll bypassJit Loon Lim2022-10-112-4/+10
* HSD #15011744436: configs: socfpga: Remove SPL SPI related configs from CVLokanathan, Raaj2022-10-111-0/+4
* spi: Remove speed and mode from spi_flash_probe_bus_csLokanathan, Raaj2022-10-062-4/+0
* test: dm: spi: Replace _spi_get_bus_and_cs() by spi_get_bus_and_cs() in some ...Patrice Chotard2022-10-061-8/+4
* spi: spi_flash_probe_bus_cs() rely on DT for spi speed and modePatrice Chotard2022-10-061-2/+16
* spi: spi-uclass: Add new spi_get_bus_and_cs() implementationPatrice Chotard2022-10-062-20/+10
* configs: socfpga: Define the correct ref clock for the QSPI driverLokanathan, Raaj2022-10-063-3/+13
* HSD 15011662064: Remove "x1" register to follow mainline changesLokanathan, Raaj2022-10-061-1/+1
* Added correction for is_ddr_init and reset_type_printLokanathan, Raaj2022-10-061-73/+27
* ddr: altera: n5x: Include DDR4 for the same hardcoding settingsTien Fong Chee2022-10-061-16/+12
* ddr: altera: n5x: Fixing debug log typoTien Fong Chee2022-10-061-4/+4
* ddr: altera: n5x: Ensure 'cal->header.data_len' is validatedTien Fong Chee2022-10-061-8/+35