| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Bump certifi from 2021.10.8 to 2022.12.7 in /doc/sphinxdependabot/pip/doc/sphinx/certifi-2022.12.7 | dependabot[bot] | 2022-12-09 | 1 | -1/+1 |
| * | HSD #18025336902: intel: n5x: ddr: update license for secure_vabrel_socfpga_v2022.07_22.12.01_pr | Lokanathan, Raaj | 2022-11-14 | 2 | -4/+4 |
| * | HSD #15011820475: arm: dts: soc64: Revert "changing DDR aliasing addresses" | Lokanathan, Raaj | 2022-11-11 | 3 | -66/+6 |
| * | altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)rel_socfpga_v2022.07_RC_22.11.02_pr | Dinesh Maniyam | 2022-10-21 | 1 | -1/+1 |
| * | jenkins: Enable PR CI/CDrel_socfpga_v2022.07_RC_22.11.01_prrel_socfpga_v2022.07_RC_22.10.02_pr | Boon Khai Ng | 2022-10-04 | 1 | -0/+242 |
| * | doc: README.socfpga: Update for U-boot 2022.07 | Lokanathan, Raaj | 2022-09-27 | 1 | -5/+5 |
| * | HSD #15011817806: fs-loader: Doc improvementrel_socfpga_v2022.07_RC_22.10.01_pr | Lokanathan, Raaj | 2022-09-26 | 1 | -0/+8 |
| * | HSD #15011817806: fs-loader: Perform code cleanups on fs-loader driver | Lokanathan, Raaj | 2022-09-26 | 4 | -16/+9 |
| * | HSD #15011860471: Remove cm_get_qspi_controller_clk_hz from socfpga_soc64_com... | Lokanathan, Raaj | 2022-09-23 | 2 | -14/+0 |
| * | HSD #15011858928: configs: Set COUNTER_FREQUENCY configurations | Lokanathan, Raaj | 2022-09-23 | 6 | -0/+6 |
| * | HSD #16018042241: arm: dts: arria10: Increase boot partition size for NANDrel_socfpga_v2022.07_RC_22.09.03_prrel_socfpga_v2022.07_RC_22.09.02_pr | Teoh Ji Sheng | 2022-09-08 | 1 | -2/+2 |
| * | HSD #18019005734: arch: arm: mach-socfpga: SDM Doorbell Issue Fix | Yuslaimi, Alif Zakuan | 2022-08-22 | 1 | -10/+5 |
| * | HSD #14016953396: rsu: ignore fw cpb errors after fixing cpbs | Radu Bacrau | 2022-08-15 | 1 | -2/+6 |
| * | HSD #14016896875: rsu: fix cpb header | Radu Bacrau | 2022-08-15 | 1 | -1/+1 |
| * | HSD #18022972407: drivers: clk: Update comment to describe pll bypass | Jit Loon Lim | 2022-08-15 | 2 | -4/+10 |
| * | HSD #15011744436: configs: socfpga: Remove SPL SPI related configs from CV | Lokanathan, Raaj | 2022-08-12 | 1 | -0/+4 |
| * | spi: Remove speed and mode from spi_flash_probe_bus_cs | Lokanathan, Raaj | 2022-08-12 | 2 | -4/+0 |
| * | test: dm: spi: Replace _spi_get_bus_and_cs() by spi_get_bus_and_cs() in some ... | Patrice Chotard | 2022-08-12 | 1 | -8/+4 |
| * | spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode | Patrice Chotard | 2022-08-12 | 1 | -2/+16 |
| * | spi: spi-uclass: Add new spi_get_bus_and_cs() implementation | Patrice Chotard | 2022-08-12 | 2 | -20/+10 |
| * | configs: socfpga: Define the correct ref clock for the QSPI driver | Lokanathan, Raaj | 2022-08-12 | 3 | -3/+14 |
| * | HSD 15011662064: Remove "x1" register to follow mainline changes | Lokanathan, Raaj | 2022-08-12 | 1 | -1/+1 |
| * | drivers: mtd: spi: Add support for MX66U1G45G SPI NOR flash | Teik Heng Chong | 2022-08-12 | 1 | -0/+2 |
| * | Added correction for is_ddr_init and reset_type_print | Lokanathan, Raaj | 2022-07-28 | 1 | -73/+27 |
| * | ddr: altera: n5x: Include DDR4 for the same hardcoding settings | Tien Fong Chee | 2022-07-28 | 1 | -16/+12 |
| * | ddr: altera: n5x: Fixing debug log typo | Tien Fong Chee | 2022-07-28 | 1 | -4/+4 |
| * | ddr: altera: n5x: Ensure 'cal->header.data_len' is validated | Tien Fong Chee | 2022-07-28 | 1 | -8/+35 |
| * | ddr: altera: n5x: Ensure correct size of result for correct type casting | Tien Fong Chee | 2022-07-28 | 1 | -4/+4 |
| * | ddr: altera: n5x: Copies calibration data to DDR when DDR retention is set | Tien Fong Chee | 2022-07-28 | 1 | -4/+7 |
| * | ddr: altera: n5x: Return error if invalid DDR type is detected in argument | Tien Fong Chee | 2022-07-28 | 1 | -0/+3 |
| * | ddr: altera: n5x: Checking DDR init hang before reset due to watchdog | Tien Fong Chee | 2022-07-28 | 1 | -8/+21 |
| * | ddr: altera: n5x: Checking DDR DBE | Tien Fong Chee | 2022-07-28 | 1 | -9/+23 |
| * | arm: socfpga: n5x: Update DDR init progress bit | Tien Fong Chee | 2022-07-28 | 1 | -0/+16 |
| * | ddr: altera: n5x: Add self-refresh support in DDR4 | Tien Fong Chee | 2022-07-28 | 2 | -42/+726 |
| * | ddr: altera: Add SDRAM driver for Intel N5X device from mainline | Lokanathan, Raaj | 2022-07-28 | 2 | -828/+97 |
| * | HSD #18020445323-10: arm: dts: soc64: Move OCRAM CCU config to DTS | Tien Fong Chee | 2022-07-28 | 3 | -18/+22 |
| * | HSD #18020445323-9: arm: dts: agilex: Add ccu_mem0_I_main QoS | Tien Fong Chee | 2022-07-28 | 1 | -0/+18 |
| * | HSD #18020445323-8: arm: dts: agilex: Add fpga2sdram FW settings | Tien Fong Chee | 2022-07-28 | 1 | -0/+32 |
| * | HSD #18020445323-7: ddr: altera: agilex: Remove code redundancy | Tien Fong Chee | 2022-07-28 | 1 | -4/+1 |
| * | HSD #18020445323-6: arm: dts: s10: Move CCU config of OCRAM to DTS | Tien Fong Chee | 2022-07-28 | 2 | -6/+4 |
| * | HSD #18020445323-5: arm: dts: s10: Add ccu_mem0_I_main QoS | Tien Fong Chee | 2022-07-28 | 1 | -0/+18 |
| * | HSD #18020445323-4: arm: dts: s10: Add fpga2sdram FW settings | Tien Fong Chee | 2022-07-28 | 1 | -0/+84 |
| * | HSD #18020445323-3: arm: dts: s10: Move CCU config of DDR to DTS | Tien Fong Chee | 2022-07-28 | 2 | -44/+27 |
| * | HSD #18020445323-2: arm: dts: Add comments for all accesses config in DTS | Tien Fong Chee | 2022-07-28 | 4 | -4/+17 |
| * | HSD #18020445323-1: doc: dtbinding: Improve doc description | Tien Fong Chee | 2022-07-28 | 1 | -12/+382 |
| * | HSD #18016393902: doc: README.socfpga: Add Git branch releases convention | Sin Hui Kho | 2022-07-28 | 1 | -11/+41 |
| * | HSD #14016754550: arch: arm: dts: Align kernel.itb load and entry address | Dinesh Maniyam | 2022-07-28 | 1 | -3/+3 |
| * | HSD #18021819983: configs: socfpga: Change load address to 0x02000000 | Dinesh Maniyam | 2022-07-28 | 7 | -0/+7 |
| * | Remove the duplicated SYS_LOAD_ADDR config from Kconfig | Lokanathan, Raaj | 2022-07-28 | 1 | -14/+0 |
| * | HSD #15011081322: arm: socfpga: Add new QSPI clock path of Linux DTB | Sin Hui Kho | 2022-07-28 | 1 | -6/+10 |
