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author | Tien Fong Chee <tien.fong.chee@intel.com> | 2023-03-08 19:20:15 +0800 |
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committer | tienfong <tien.fong.chee@gmail.com> | 2023-03-20 11:03:15 +0800 |
commit | 61ae22e548ebda525d5216d107e45f20eca70537 (patch) | |
tree | 0e745b35fa0bf99661cd668ef81ee375b40003e7 /configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | |
parent | 1dda7c081ee51d6c4b52d2ef773464b745fb9ec0 (diff) | |
download | u-boot-socfpga-socfpga_v2022.10.tar.gz |
HSD #15012965144: doc: README.socfpga: Add FPGA full reconfiguration flowHEADrel_socfpga_v2022.10_23.05.01_prrel_socfpga_v2022.10_23.04.02_prrel_socfpga_v2022.10_23.04.01_prQPDS23.1_REL_GSRD_PRsocfpga_v2022.10
Adding required steps of running proper FPGA full reconfiguration. These
steps are required to ensure all all outstanding traffic between MPFE to
bridge and FPGA to bridge are completed before FPGA configuration.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig')
0 files changed, 0 insertions, 0 deletions