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| author | Thor Thayer <thor.thayer@linux.intel.com> | 2019-12-06 11:11:19 -0600 |
|---|---|---|
| committer | Thor Thayer <thor.thayer@linux.intel.com> | 2019-12-06 11:11:19 -0600 |
| commit | 2952f2d2fd0415c0fb2a12494854d02265dc6464 (patch) | |
| tree | dc0c3efe9b19be44c687b2f6411b1dc0c56c9371 | |
| parent | a76dcc03f6fd307fca42d58e5f149e5c0078f929 (diff) | |
| download | u-boot-socfpga-rel_socfpga_v2017.09_20.03.02_rc1.tar.gz | |
HSD #1707128118: Enable Non-Secure SDRAM ECC Register Accessrel_socfpga_v2017.09_20.06.01_rc1rel_socfpga_v2017.09_20.06.01_prrel_socfpga_v2017.09_20.05.02_rc1rel_socfpga_v2017.09_20.05.02_prrel_socfpga_v2017.09_20.05.01_rc1rel_socfpga_v2017.09_20.05.01_prrel_socfpga_v2017.09_20.04.03_rc1rel_socfpga_v2017.09_20.04.03_prrel_socfpga_v2017.09_20.04.02_rc1rel_socfpga_v2017.09_20.04.02_prrel_socfpga_v2017.09_20.04.01_rc1rel_socfpga_v2017.09_20.04.01_prrel_socfpga_v2017.09_20.03.02_rc1rel_socfpga_v2017.09_20.03.02_prrel_socfpga_v2017.09_20.03.01_rc1rel_socfpga_v2017.09_20.03.01_prrel_socfpga_v2017.09_20.02.02_rc1rel_socfpga_v2017.09_20.02.02_prrel_socfpga_v2017.09_20.02.01_rc1rel_socfpga_v2017.09_20.02.01_prrel_socfpga_v2017.09_20.01.02_rc1rel_socfpga_v2017.09_20.01.02_prrel_socfpga_v2017.09_20.01.01_rc1rel_socfpga_v2017.09_20.01.01_prrel_socfpga_v2017.09_19.12.02_rc1rel_socfpga_v2017.09_19.12.02_pr
The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.
The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
| -rwxr-xr-x | drivers/ddr/altera/sdram_s10.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 276ca212cc..f606525659 100755 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -533,9 +533,6 @@ static int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS); - /* Enable non-secure writes to HMC Adapter for SDRAM ECC */ - writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); - /* Initialize memory content if not from warm reset */ if (!cpu_has_been_warmreset()) sdram_init_ecc_bits(&bd); @@ -549,6 +546,10 @@ static int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } + /* Enable non-secure read/writes to HMC Adapter for SDRAM ECC */ + writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); + + sdram_size_check(&bd); priv->info.base = bd.bi_dram[0].start; |