FogBugz #100359: Review - Add OSE support and fix debug mode build errorrel_ghrd_RC9rel_ghrd_RC8rel_ghrd_RC6rel_ghrd_RC5rel_ghrd_RC4rel_ghrd_RC3rel_ghrd_RC2rel_ghrd_RC10rel_ghrd_RC1rel_13.02_RC9rel_13.02_RC8rel_13.02_RC7rel_13.02_RC6rel_13.02_RC10

Add OSE support and fix debug mode build error

Signed-off-by: Chin Liang See <clsee@altera.com>

10 files changed, 27 insertions, 54 deletions

diff --git a/arch/arm/cpu/armv7/socfpga/debug_memory.c b/arch/arm/cpu/armv7/socfpga/debug_memory.c
index e7e092f0b1..f80151195e 100644
--- a/arch/arm/cpu/armv7/socfpga/debug_memory.c
+++ b/arch/arm/cpu/armv7/socfpga/debug_memory.c
@@ -151,28 +151,7 @@ int svc(unsigned operation, void *value)
 /* perform a write to console buffer */
 int semihosting_write(const char *buffer)
 {
-#if 0
-	struct struct_semihosting_write s_semihosting_write;
-
-	/* open the write channel */
-	if(semihosting_write_handler==0)
-	{
-		struct struct_semihosting_open s_semihosting_open;
-		char *handle=":tt";
-		s_semihosting_open.file = handle;
-		s_semihosting_open.permissions = 0;	/* "r" mode */
-		s_semihosting_open.length = 3;
-		semihosting_write_handler = svc(0x1,&s_semihosting_open);
-	}
-
-	/* write to console buffer */
-	s_semihosting_write.handle = semihosting_write_handler;
-	s_semihosting_write.buffer = (char *)buffer;
-	s_semihosting_write.length = SEMI_LENGTH;
-	return svc(0x5, &s_semihosting_write);
-#else
 	return svc(SEMI_PRINTF, (void *)buffer);
-#endif
 }
 
 #endif
diff --git a/arch/arm/cpu/armv7/socfpga/sdram.c b/arch/arm/cpu/armv7/socfpga/sdram.c
index dc1d2beb8f..148dac796c 100644
--- a/arch/arm/cpu/armv7/socfpga/sdram.c
+++ b/arch/arm/cpu/armv7/socfpga/sdram.c
@@ -62,6 +62,9 @@ void irq_handler_ecc_sdram(void *arg)
 #endif /* CONFIG_SPL_BUILD */
 }
 
+
+#ifdef CONFIG_SPL_BUILD
+
 /* Function to update the field within variable */
 unsigned sdram_write_register_field (unsigned masked_value,
 	unsigned data, unsigned shift, unsigned mask)
@@ -1015,3 +1018,5 @@ unsigned sdram_calibration_full(void)
 	return sdram_calibration();
 }
 
+#endif	/* CONFIG_SPL_BUILD */
+
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index df146e3dd2..3a7834375d 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -168,9 +168,7 @@ void spl_board_init(void)
 	WATCHDOG_RESET();
 #endif
 	DEBUG_MEMORY
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	debug("Freezing all I/O banks\n");
-#endif
 	/* freeze all IO banks */
 	sys_mgr_frzctrl_freeze_req(FREEZE_CHANNEL_0,
 		FREEZE_CONTROLLER_FSM_SW);
@@ -187,9 +185,7 @@ void spl_board_init(void)
 	WATCHDOG_RESET();
 #endif
 	DEBUG_MEMORY
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	debug("Asserting reset to all except L4WD and SDRAM\n");
-#endif
 	/*
 	 * assert all peripherals and bridges to reset. This is
 	 * to ensure no glitch happen during PLL re-configuration
@@ -200,9 +196,7 @@ void spl_board_init(void)
 #endif
 
 	DEBUG_MEMORY
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	debug("Deassert reset for OSC1 Timer\n");
-#endif
 	/*
 	 * deassert reset for osc1timer0. We need this for delay
 	 * function that required during PLL re-configuration
@@ -210,9 +204,7 @@ void spl_board_init(void)
 	reset_deassert_osc1timer0();
 
 	DEBUG_MEMORY
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	debug("Init timer\n");
-#endif
 	/* init timer for enabling delay function */
 	timer_init();
 
@@ -222,9 +214,7 @@ void spl_board_init(void)
 	WATCHDOG_RESET();
 #endif
 	DEBUG_MEMORY
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	debug("Reconfigure Clock Manager\n");
-#endif
 	/* reconfigure the PLLs */
 	cm_basic_init(&cm_default_cfg);
 
@@ -243,9 +233,7 @@ void spl_board_init(void)
 		setbits_le32(CONFIG_SYSMGR_ROMCODEGRP_CTRL,
 			SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 #endif /* CONFIG_PRELOADER_BOOTROM_HANDSHAKE_CFGIO */
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 		debug("Configure IOCSR\n");
-#endif
 		/* configure the IOCSR through scan chain */
 		scan_mgr_io_scan_chain_prg(
 			IO_SCAN_CHAIN_0,
@@ -306,9 +294,7 @@ void spl_board_init(void)
 	WATCHDOG_RESET();
 #endif
 	DEBUG_MEMORY
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	debug("Deasserting resets\n");
-#endif
 	/* de-assert reset for peripherals and bridges based on handoff */
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
 	reset_deassert_peripherals_handoff();
@@ -325,9 +311,7 @@ void spl_board_init(void)
 	WATCHDOG_RESET();
 #endif
 	DEBUG_MEMORY
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	debug("Unfreezing/Thaw all I/O banks\n");
-#endif
 	/* unfreeze / thaw all IO banks */
 	sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_0,
 		FREEZE_CONTROLLER_FSM_SW);
@@ -359,9 +343,7 @@ void spl_board_init(void)
 	WATCHDOG_RESET();
 #endif
 	DEBUG_MEMORY
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	puts("SDRAM : Initializing MMR registers\n");
-#endif
 	/* SDRAM MMR initialization */
 	if (sdram_mmr_init_full() != 0)
 		hang();
@@ -370,9 +352,7 @@ void spl_board_init(void)
 	WATCHDOG_RESET();
 #endif
 	DEBUG_MEMORY
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	puts("SDRAM : Calibrationg PHY\n");
-#endif
 	/* SDRAM calibration */
 	if (sdram_calibration_full() == 0)
 		hang();
@@ -388,11 +368,9 @@ void spl_board_init(void)
 
 
 #ifdef CONFIG_USE_IRQ
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	debug("Setup interrupt controller... IRQ SP at 0x%08x "
 		"with size 0x%08x\n", __irq_stack_start,
 		CONFIG_STACKSIZE_IRQ);
-#endif
 	/* setup the stack pointer for IRQ */
 	gd->irq_sp = (unsigned long)&__irq_stack_start;
 	DEBUG_MEMORY
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
index bbead45672..cb16a66460 100644
--- a/arch/arm/cpu/armv7/socfpga/timer.c
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -80,14 +80,15 @@ ulong get_timer_masked(void)
 {
 	/* current tick value */
 	ulong now = read_timer() /
-		(CONFIG_TIMER_CLOCK_KHZ*1000 / CONFIG_SYS_HZ);
+		(CONFIG_TIMER_CLOCK_KHZ * 1000 / CONFIG_SYS_HZ);
 	if (gd->lastinc >= now) {
 		/* normal mode (non roll) */
 		/* move stamp forward with absolute diff ticks */
 		gd->tbl += gd->lastinc - now;
 	} else {
 		/* we have overflow of the count down timer */
-		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+		gd->tbl += (TIMER_LOAD_VAL / (CONFIG_TIMER_CLOCK_KHZ * 1000
+			/ CONFIG_SYS_HZ)) - gd->lastinc + now;
 	}
 	gd->lastinc = now;
 	return gd->tbl;
@@ -100,7 +101,7 @@ void reset_timer(void)
 {
 	/* capture current decrementer value time */
 	gd->lastinc = read_timer() /
-		(CONFIG_TIMER_CLOCK_KHZ*1000 / CONFIG_SYS_HZ);
+		(CONFIG_TIMER_CLOCK_KHZ * 1000 / CONFIG_SYS_HZ);
 	/* start "advancing" time stamp from 0 */
 	gd->tbl = 0;
 }
@@ -129,7 +130,7 @@ ulong get_timer_count_masked(void)
 
 ulong get_timer_count(ulong base)
 {
-	return get_timer_masked() - base;
+	return get_timer_count_masked() - base;
 }
 
 /*
diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/include/asm/arch-socfpga/sdram.h
index 022c69b814..de9f642c67 100644
--- a/arch/arm/include/asm/arch-socfpga/sdram.h
+++ b/arch/arm/include/asm/arch-socfpga/sdram.h
@@ -29,9 +29,10 @@ extern unsigned long irq_cnt_ecc_sdram;
 
 /* function declaration */
 void irq_handler_ecc_sdram(void *arg);
+#ifdef CONFIG_SPL_BUILD
 unsigned sdram_mmr_init_full(void);
 unsigned sdram_calibration_full(void);
-
+#endif
 
 /* Group: sdr.phygrp.sccgrp                                                */
 #define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile
index d71e682f8b..3df3b1bcd3 100644
--- a/board/altera/socfpga_cyclone5/Makefile
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -26,8 +26,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= socfpga_cyclone5.o pinmux_config.o iocsr_config.o
+COBJS-y := socfpga_cyclone5.o
+COBJS-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/board/altera/socfpga_cyclone5/sdram/Makefile b/board/altera/socfpga_cyclone5/sdram/Makefile
index 55e4a48f92..4508cdd69c 100644
--- a/board/altera/socfpga_cyclone5/sdram/Makefile
+++ b/board/altera/socfpga_cyclone5/sdram/Makefile
@@ -26,9 +26,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)libsocfpga-sdram.o
 
-COBJS	:= sequencer.o tclrpt.o
-COBJS	+= sequencer_auto_ac_init.o sequencer_auto_inst_init.o
+COBJS-$(CONFIG_SPL_BUILD):= sequencer.o tclrpt.o
+COBJS-$(CONFIG_SPL_BUILD)+= sequencer_auto_ac_init.o sequencer_auto_inst_init.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/common/console.c b/common/console.c
index 60077197b5..7828d5b375 100644
--- a/common/console.c
+++ b/common/console.c
@@ -410,10 +410,12 @@ void puts(const char *s)
 		fputs(stdout, s);
 	} else {
 		/* Send directly to the handler */
-#ifdef CONFIG_SPL_SEMIHOSTING_SUPPORT
 		if (gd->have_console)
-#endif
+#if !defined(CONFIG_SPL_BUILD) | defined(CONFIG_SPL_SERIAL_SUPPORT)
 			serial_puts(s);
+#else
+			;	/* no printout */
+#endif
 #ifdef CONFIG_SPL_SEMIHOSTING_SUPPORT
 		semihosting_write(s);
 #endif
diff --git a/drivers/mmc/spl_mmc.c b/drivers/mmc/spl_mmc.c
index 15e3c72876..4f9b4a45e4 100644
--- a/drivers/mmc/spl_mmc.c
+++ b/drivers/mmc/spl_mmc.c
@@ -75,6 +75,7 @@ static void mmc_load_image_mbr(struct mmc *mmc)
 #define MBR_PARTITION_TYPE_OFFSET		(4)
 #define MBR_PARTITION_START_SECTOR_OFFSET	(8)
 #define MBR_PARTITION_ENTRY_SIZE		(16)
+#define CONFIG_SYS_MMCSD_MBR_MODE_U_BOOT_PARTITION_ID	(0xA2)
 
 	u32 i;
 	u32 part_type;
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 829a8ebece..4174a21e47 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -147,6 +147,10 @@
 #undef CONFIG_PARTITIONS
 #endif
 
+/* OSE operating system support */
+#define CONFIG_BOOTM_OSE
+
+
 /*
  * Environment setup
  */
@@ -547,7 +551,6 @@
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR \
 	(CONFIG_PRELOADER_SDMMC_NEXT_BOOT_IMAGE / 512)
-#define CONFIG_SYS_MMCSD_MBR_MODE_U_BOOT_PARTITION_ID	(0xA2)
 #endif
 
 /*