diff options
Diffstat (limited to 'board/amlogic/g12a_u211_v1/firmware/timing.c')
| -rw-r--r-- | board/amlogic/g12a_u211_v1/firmware/timing.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/board/amlogic/g12a_u211_v1/firmware/timing.c b/board/amlogic/g12a_u211_v1/firmware/timing.c index 4d7632e79e..d91893eb10 100644 --- a/board/amlogic/g12a_u211_v1/firmware/timing.c +++ b/board/amlogic/g12a_u211_v1/firmware/timing.c @@ -78,8 +78,8 @@ ddr_set_t __ddr_setting[] = { .dram_cs0_size_MB = 0xffff, .dram_cs1_size_MB = 0, .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0d0d, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -147,8 +147,8 @@ ddr_set_t __ddr_setting[] = { .dram_cs0_size_MB = 0xffff, .dram_cs1_size_MB = 0xffff, .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0c0c, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -230,8 +230,8 @@ ddr_set_t __ddr_setting[] = { .dram_cs0_size_MB = 0xffff,//1024, .dram_cs1_size_MB = 0xffff,//1024, .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0808, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -303,8 +303,8 @@ ddr_set_t __ddr_setting[] = { .dram_cs0_size_MB = 0xffff,//1024, .dram_cs1_size_MB = 0,//1024, .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0808, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -374,8 +374,8 @@ ddr_set_t __ddr_setting[] = { .dram_cs0_size_MB = 0xffff,//1024, .dram_cs1_size_MB = 0xffff,//1024, .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x00c, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm |