ddr: timing: G12A/G12B/TL1 LPDDR4_PHY_V_0_1_11_driver_update_bl33 [3/3]

PD#SWPL-3642

Problem:
LPDDR4_PHY_V_0_1_10_driver_update
LPDDR4_PHY_V_0_1_11_driver_update

Solution:
1)
DDR_DRIVER_VERSION "LPDDR4_PHY_V_0_1_10" 20181106-20181116
1 add tl1 read read-dbi function
2 change ddr3 trrd parameter over 912 to 8.5ns for hynix ddr3
3 repair lpddr3/4 ck driver strength setting
4 add dmctest write D8-D15 register ,add bit data pattern
5 enable ddr3/ddr4 asr ddr auto refresh function

DDR_DRIVER_VERSION "LPDDR4_PHY_V_0_1_11" 20181117-20181214
1 add boot times
2 modify ddr4 apd to dfi clk on /ddr3 txpdll register
3 add uboot real window test
4 adjust auto scan driver interface
5 add ddr vco frequency formula repair some frequency calculate error
6 repair lpddr4 init dram vref value calculate error
7 modify ddr3 trrd for hynix ddr3 high frequency fail
8 update ProcOdtTimeCtl formula
9 add tl1 lpddr4 16bit mode
10 modify some c-function for reduce code size

2)x301 need The same ota or img can run at DDR3 and LPDDR4

3)ddr_tRRDS modify from 6000 to 8500
QPL.U212.MT41K256M16TW-107P max freq from 1128 to 1224MHz

Verify:
test pass at U212/T203/W400/X301.

Change-Id: Ie4aeb2722c9eee0b475a82830225a2768e508e44
Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com>

0 files changed, 0 insertions, 0 deletions