ODROID-N2L: Introduce new SBC board 'ODROID-N2L'

  N2L U-Boot build :
	# make odroidn2l_defconfig
	# make

Signed-off-by: ckkim <changkon12@gmail.com>
Change-Id: I49a43777cfb083965e7efc9fa8dd4b357777ec28

8 files changed, 150 insertions, 4 deletions

diff --git a/board/amlogic/Kconfig b/board/amlogic/Kconfig
index 709b992b0e..915ba7e326 100644
--- a/board/amlogic/Kconfig
+++ b/board/amlogic/Kconfig
@@ -274,6 +274,11 @@ config ODROID_N2
 	select ODROID_COMMON
 	default n
 
+config ODROID_N2L
+	bool "Support Hardkernel ODROID-N2L board"
+	select ODROID_COMMON
+	default n
+
 config ODROID_C4
 	bool "Support Hardkernel ODROID-C4 board"
 	select ODROID_COMMON
@@ -540,6 +545,10 @@ if ODROID_N2
 source "board/hardkernel/odroidn2/Kconfig"
 endif
 
+if ODROID_N2L
+source "board/hardkernel/odroidn2/Kconfig"
+endif
+
 if ODROID_C4
 source "board/hardkernel/odroidc4/Kconfig"
 endif
diff --git a/board/hardkernel/odroid-common/board.c b/board/hardkernel/odroid-common/board.c
index ae71054cba..fd72464c2b 100644
--- a/board/hardkernel/odroid-common/board.c
+++ b/board/hardkernel/odroid-common/board.c
@@ -72,6 +72,13 @@ static unsigned int get_hw_revision(void)
 	} else if (IS_RANGE(adc, 500, 520)) {
 		hwrev = BOARD_REVISION(2021,  1, 21);
 	}
+#elif defined(CONFIG_ODROID_N2L)
+	/* ODROID-N2lite rev_0.1 */
+	if (IS_RANGE(adc, 410, 430)) {		/* avg : 419 */
+		hwrev = BOARD_REVISION(2022, 2, 18);
+	} else {
+		hwrev = BOARD_REVISION(2022, 2, 18);
+	}
 #elif defined(CONFIG_ODROID_C4)
 	if (IS_RANGE(adc, 80, 100))	/* avg : 90 */
 		hwrev = BOARD_REVISION(2020, 1, 29);
@@ -105,7 +112,7 @@ void board_set_dtbfile(const char *format)
 	setenv("fdtfile", s);
 }
 
-#if defined(CONFIG_ODROID_N2)
+#if defined(CONFIG_ODROID_N2) || defined(CONFIG_ODROID_N2L)
 int board_is_odroidn2(void)
 {
 	int hwrev = board_revision();
@@ -120,6 +127,14 @@ int board_is_odroidn2plus(void)
 {
 	return !board_is_odroidn2();
 }
+
+int board_is_odroidn2l(void)
+{
+	int hwrev = board_revision();
+
+	return ((hwrev >= BOARD_REVISION(2022, 2, 18)) ? 1 : 0);
+}
+
 #elif defined(CONFIG_ODROID_C4)
 int board_is_odroidc4(void)
 {
diff --git a/board/hardkernel/odroid-common/odroid-common.h b/board/hardkernel/odroid-common/odroid-common.h
index 79c3d62f32..0293c8e3a8 100644
--- a/board/hardkernel/odroid-common/odroid-common.h
+++ b/board/hardkernel/odroid-common/odroid-common.h
@@ -30,9 +30,10 @@ extern int get_adc_value(int channel);
 int board_revision(void);
 void board_set_dtbfile(const char *format);
 
-#if defined(CONFIG_ODROID_N2)
+#if defined(CONFIG_ODROID_N2) || defined(CONFIG_ODROID_N2L)
 int board_is_odroidn2(void);
 int board_is_odroidn2plus(void);
+int board_is_odroidn2l(void);
 #elif defined(CONFIG_ODROID_C4)
 int board_is_odroidc4(void);
 int board_is_odroidhc4(void);
diff --git a/board/hardkernel/odroidn2/firmware/timing.c b/board/hardkernel/odroidn2/firmware/timing.c
index 6801380ba7..4ac3287257 100644
--- a/board/hardkernel/odroidn2/firmware/timing.c
+++ b/board/hardkernel/odroidn2/firmware/timing.c
@@ -76,6 +76,84 @@
 #define CONFIG_DDR4_DEFAULT_CLK		1320
 
 ddr_set_t __ddr_setting[] = {
+#if defined(CONFIG_ODROID_N2L)
+{
+	/*odroid-n2-lite lpddr4x lpddr4 */
+	.board_id			= CONFIG_BOARD_ID_MASK,
+	.version			= 1,
+	//.dram_rank_config		= CONFIG_DDR0_32BIT_RANK0_CH0,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH01,
+	.ddr_rfc_type			= DDR_RFC_TYPE_LPDDR4_8Gbx1,
+	.DramType			= CONFIG_DDR_TYPE_LPDDR4,
+	.DRAMFreq			= {1200, 0, 0, 0},
+	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
+	.ddr_start_offset		= CFG_DDR_START_OFFSET,
+	.imem_load_addr			= 0xFFFC0000, //sram
+	.dmem_load_size			= 0x1000, //4K
+
+	.DisabledDbyte			= 0xf0,
+	.Is2Ttiming			= 0,
+	.HdtCtrl			= 0xa,
+	.dram_cs0_size_MB		= 0xffff,//1024,
+	.dram_cs1_size_MB		= 0xffff,//1024,
+	.training_SequenceCtrl		= {0x131f,0x61}, //ddr3 0x21f 0x31f
+	.phy_odt_config_rank		= {0x23,0x13}, //use 0x23 0x13  compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+	.dfi_odt_config			= 0x0d0d,  //use 0d0d compatibility with 1rank and 2rank  //0808
+	.PllBypassEn			= 0, //bit0-ps0,bit1-ps1
+	.ddr_rdbi_wr_enable		= 0,
+	.clk_drv_ohm			= 40,
+	.cs_drv_ohm			= 40,
+	.ac_drv_ohm			= 40,
+	.soc_data_drv_ohm_p		= 40,
+	.soc_data_drv_ohm_n		= 40,
+	.soc_data_odt_ohm_p		= 0,
+	.soc_data_odt_ohm_n		= 120,
+	.dram_data_drv_ohm		= 40, //lpddr4 sdram only240/1-6
+	.dram_data_odt_ohm		= 120,
+	.dram_ac_odt_ohm		= 120,
+	.lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq     0 2/5 vddq
+	.soc_clk_slew_rate		= 0x3ff,//0x253,
+	.soc_cs_slew_rate		= 0x100,//0x253,
+	.soc_ac_slew_rate		= 0x100,//0x253,
+	.soc_data_slew_rate		= 0x1ff,
+	.vref_output_permil		= 350,//200,
+	.vref_receiver_permil		= 0,
+	.vref_dram_permil		= 0,
+	//.vref_reverse			= 0,
+	.ac_trace_delay			= {00,0x0,0,0,0,0,0x0,00},
+	//.ac_trace_delay		= {32,32,32,32,32,32,32,32,32,32},
+	.ac_pinmux			= {00,00},
+	.ddr_dmc_remap			= {
+						[0] = ( 5 |  6 << 5 |  7 << 10 |  8<< 15 | 9<< 20 | 10 << 25 ),
+						[1] = ( 11|  0 << 5 |  0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+						[2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+						[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+						[4] = ( 30| 12 << 5 | 13 << 10 |  14<< 15 |  0 << 20 |  0 << 25 ),
+	},
+	.ddr_lpddr34_ca_remap	= {00,00},
+	.ddr_lpddr34_dq_remap	= {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
+	.dram_rtt_nom_wr_park	= {00,00},
+
+	/* pll ssc config:
+	 *
+	 *   pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+	 *      ppm = strength * 500
+	 *      mode: 0=center, 1=up, 2=down
+	 *
+	 *   eg:
+	 *     1. config 1000ppm center ss. then mode=0, strength=2
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+	 *     2. config 3000ppm down ss. then mode=2, strength=6
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+	 */
+	.pll_ssc_mode		= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+	.ddr_func		= DDR_FUNC,
+	.magic			= DRAM_CFG_MAGIC,
+	.diagnose		= CONFIG_DIAGNOSE_DISABLE,
+	.bitTimeControl_2d      = 1,
+	.fast_boot[0]		= 1,
+},
+#else
 {
 	/* odroid-n2 ddr4 : (4Gbitx2)x2, (8Gbitx2)x2 */
 	.board_id			= CONFIG_BOARD_ID_MASK,
@@ -192,6 +270,7 @@ ddr_set_t __ddr_setting[] = {
 	.ddr_func			= DDR_FUNC,
 	.magic				= DRAM_CFG_MAGIC,
 },
+#endif
 };
 
 pll_set_t __pll_setting = {
@@ -268,6 +347,10 @@ ddr_reg_t __ddr_reg[] = {
 	#error "VCCK val out of range\n"
 #endif
 
+#if defined(CONFIG_ODROID_N2L)
+	#define VDDEE_VAL_REG0	0x0002000e
+	#define VDDEE_VAL_REG1	0x0002000e
+#else
 /* VDDEE_VAL_REG0: VDDEE PWM table  0.69v-0.862v*/
 /* VDDEE_VAL_REG1: VDDEE PWM table  0.69v-0.863v*/
 #if    (VDDEE_VAL == 800)
@@ -294,6 +377,7 @@ ddr_reg_t __ddr_reg[] = {
 #else
 	#error "VDDEE val out of range\n"
 #endif
+#endif
 
 /* for PWM use */
 /* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
diff --git a/board/hardkernel/odroidn2/odroidn2.c b/board/hardkernel/odroidn2/odroidn2.c
index be391e9de7..34fb380c88 100644
--- a/board/hardkernel/odroidn2/odroidn2.c
+++ b/board/hardkernel/odroidn2/odroidn2.c
@@ -116,8 +116,10 @@ int board_eth_init(bd_t *bis)
 	dwmac_meson_cfg_drive_strength();
 	setup_net_chip_ext();
 #endif
+#if !defined(CONFIG_ODROID_N2L)
 	udelay(1000);
 	designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+#endif
 	return 0;
 }
 
@@ -278,9 +280,10 @@ static void gpio_set_vbus_power(char is_power_on)
 {
 	int ret;
 
+#if !defined(CONFIG_ODROID_N2L)
 	/* USB Host power enable/disable */
 	usbhost_set_power(is_power_on);
-
+#endif
 	/* usb otg power enable */
 	ret = gpio_request(CONFIG_USB_GPIO_PWR,
 			CONFIG_USB_GPIO_PWR_NAME);
@@ -416,9 +419,13 @@ int board_late_init(void)
 	}
 #endif
 
+#if defined(CONFIG_ODROID_N2L)
+	setenv("variant", board_is_odroidn2l() ? "n2l" : "n2");
+	board_set_dtbfile("meson64_odroid%s.dtb");
+#else
 	setenv("variant", board_is_odroidn2plus() ? "n2_plus" : "n2");
 	board_set_dtbfile("meson64_odroid%s.dtb");
-
+#endif
 	/* boot logo display - 1080p60hz */
 	run_command("showlogo", 0);
 
diff --git a/configs/odroidn2l_defconfig b/configs/odroidn2l_defconfig
new file mode 100755
index 0000000000..9ee55e271e
--- /dev/null
+++ b/configs/odroidn2l_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12B=y
+CONFIG_ODROID_N2L=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/fip/Makefile b/fip/Makefile
index b374bd63a8..abdb6bbf29 100644
--- a/fip/Makefile
+++ b/fip/Makefile
@@ -128,6 +128,19 @@ endif
 	$(call encrypt_step, --bl2sig \
 			--input $(buildtree)/fip/bl2_new.bin \
 			--output $(buildtree)/fip/bl2.n.bin.sig)
+
+ifeq ($(CONFIG_ODROID_N2L),y)
+	$(call encrypt_step,--bootmk $(FIP_BL32_PROCESS) $(V3_PROCESS_FLAG) \
+			--bl2 $(buildtree)/fip/bl2.n.bin.sig \
+			--bl30 $(buildtree)/fip/bl30_new.bin.enc \
+			--bl31 $(buildtree)/fip/bl31.$(BL3X_SUFFIX).enc \
+			--bl33 $(buildtree)/fip/bl33.bin.enc \
+			--ddrfw1 $(buildsrc)/fip/$(SOC)/lpddr4_1d.fw \
+			--ddrfw2 $(buildsrc)/fip/$(SOC)/lpddr4_2d.fw \
+			--ddrfw4 $(buildsrc)/fip/$(SOC)/piei.fw \
+			--ddrfw8 $(buildsrc)/fip/$(SOC)/$(DDR_FW_NAME) \
+			--output $(FUSING_FOLDER)/u-boot.bin)
+else
 	$(call encrypt_step,--bootmk $(FIP_BL32_PROCESS) $(V3_PROCESS_FLAG) \
 			--bl2 $(buildtree)/fip/bl2.n.bin.sig \
 			--bl30 $(buildtree)/fip/bl30_new.bin.enc \
@@ -138,6 +151,8 @@ endif
 			--ddrfw4 $(buildsrc)/fip/$(SOC)/piei.fw \
 			--ddrfw8 $(buildsrc)/fip/$(SOC)/$(DDR_FW_NAME) \
 			--output $(FUSING_FOLDER)/u-boot.bin)
+endif
+
 ifeq ($(CONFIG_AML_CRYPTO_UBOOT),y)
 	$(call encrypt_step, --efsgen --amluserkey $(AML_USER_KEY) \
 			--output $(buildtree)/fip/u-boot.bin.encrypt.efuse $(V3_PROCESS_FLAG))
diff --git a/include/configs/odroidn2.h b/include/configs/odroidn2.h
index 909106decb..381593d0bb 100644
--- a/include/configs/odroidn2.h
+++ b/include/configs/odroidn2.h
@@ -25,4 +25,12 @@
 	#define CONFIG_USB_GPIO_PWR_NAME	"GPIOH_6"
 #endif
 
+#if defined(CONFIG_ODROID_N2L)
+#define CONFIG_ETHERNET_NONE
+#undef ETHERNET_EXTERNAL_PHY
+#undef ETHERNET_INTERNAL_PHY
+
+#undef CONFIG_AML_CVBS
+#endif
+
 #endif