DMI: Adjusting structures size / Adding cpu core

This patch adds some correction of the dmi structures but also add the
support of the cpu cores/threads.

4 files changed, 70 insertions, 22 deletions

diff --git a/com32/gpllib/dmi/dmi.c b/com32/gpllib/dmi/dmi.c
index 507b11ac..ef84e1e8 100644
--- a/com32/gpllib/dmi/dmi.c
+++ b/com32/gpllib/dmi/dmi.c
@@ -299,6 +299,35 @@ static void dmi_base_board_features(uint8_t code, s_dmi * dmi)
     }
 }
 
+static void dmi_base_board_type(uint8_t code, s_dmi * dmi)
+{
+    /* 3.3.3.2 */
+    static const char *type[] = {
+            "Unknown", /* 0x01 */
+            "Other",
+            "Server Blade",
+            "Connectivity Switch",
+            "System Management Module",
+            "Processor Module",
+            "I/O Module",
+            "Memory Module",
+            "Daughter Board",
+            "Motherboard",
+            "Processor+Memory Module",
+            "Processor+I/O Module",
+            "Interconnect Board" /* 0x0D */
+    };
+
+    if (code >= 0x01 && code <= 0x0D) {
+	strlcpy(dmi->base_board.type, type[code],
+		sizeof(dmi->base_board.type));
+    } else {
+	strlcpy(dmi->base_board.type, out_of_spec,
+		sizeof(dmi->base_board.type));
+    }
+    return;
+}
+
 static void dmi_processor_voltage(uint8_t code, s_dmi * dmi)
 {
     /* 3.3.5.4 */
@@ -652,8 +681,7 @@ void dmi_decode(struct dmi_header *h, uint16_t ver, s_dmi * dmi)
 	dmi_base_board_features(data[0x09], dmi);
 	strlcpy(dmi->base_board.location, dmi_string(h, data[0x0A]),
 		sizeof(dmi->base_board.location));
-	strlcpy(dmi->base_board.type, dmi_string(h, data[0x0D]),
-		sizeof(dmi->base_board.type));
+	dmi_base_board_type(data[0x0D], dmi);
 	if (h->length < 0x0F + data[0x0E] * sizeof(uint16_t))
 	    break;
 	break;
@@ -743,6 +771,14 @@ void dmi_decode(struct dmi_header *h, uint16_t ver, s_dmi * dmi)
 		sizeof(dmi->processor.asset_tag));
 	strlcpy(dmi->processor.part_number, dmi_string(h, data[0x22]),
 		sizeof(dmi->processor.part_number));
+        dmi->processor.core_count = 0;
+        dmi->processor.core_enabled = 0;
+        dmi->processor.thread_count = 0;
+	if (h->length < 0x28)
+	    break;
+        dmi->processor.core_count = data[0x23];
+        dmi->processor.core_enabled = data[0x24];
+        dmi->processor.thread_count = data[0x25];
 	break;
     case 6:			/* 3.3.7 Memory Module Information */
 	if (h->length < 0x0C)
diff --git a/com32/gpllib/dmi/dmi_cache.c b/com32/gpllib/dmi/dmi_cache.c
index 4c3f83ce..67a43d0b 100644
--- a/com32/gpllib/dmi/dmi_cache.c
+++ b/com32/gpllib/dmi/dmi_cache.c
@@ -125,10 +125,15 @@ const char *dmi_cache_associativity(uint8_t code)
 	"4-way Set-associative",
 	"Fully Associative",
 	"8-way Set-associative",
-	"16-way Set-associative"	/* 0x08 */
+	"16-way Set-associative",	/* 0x08 */
+	"12-way Set-associative",
+	"24-way Set-associative",
+	"32-way Set-associative",
+	"48-way Set-associative",
+	"64-way Set-associative"	/* 0x0D */
     };
 
-    if (code >= 0x01 && code <= 0x08)
+    if (code >= 0x01 && code <= 0x0D)
 	return type[code - 0x01];
     return out_of_spec;
 }
diff --git a/com32/gpllib/dmi/dmi_memory.c b/com32/gpllib/dmi/dmi_memory.c
index 21458293..36937539 100644
--- a/com32/gpllib/dmi/dmi_memory.c
+++ b/com32/gpllib/dmi/dmi_memory.c
@@ -124,10 +124,15 @@ const char *dmi_memory_device_type(uint8_t code)
 	"RDRAM",
 	"DDR",
 	"DDR2",
-	"DDR2 FB-DIMM"		/* 0x14 */
+	"DDR2 FB-DIMM",		/* 0x14 */
+	NULL,
+	NULL,
+	NULL,
+	"DDR3",			/* 0x18 */
+	"FBD2"			/* 0x19 */
     };
 
-    if (code >= 0x01 && code <= 0x14)
+    if (code >= 0x01 && code <= 0x19)
 	return type[code - 0x01];
     return out_of_spec;
 }
diff --git a/com32/gpllib/dmi/dmi_processor.c b/com32/gpllib/dmi/dmi_processor.c
index 1cd9d1ba..fe2ef63a 100644
--- a/com32/gpllib/dmi/dmi_processor.c
+++ b/com32/gpllib/dmi/dmi_processor.c
@@ -49,6 +49,7 @@ const char *dmi_processor_type(uint8_t code)
 const char *dmi_processor_family(uint8_t code, char *manufacturer)
 {
     /* 3.3.5.2 */
+    /* TODO : Need to implement code/value (see dmidecode) insteed of array to address large index */
     static const char *family[256] = {
 	NULL,			/* 0x00 */
 	"Other",
@@ -221,11 +222,11 @@ const char *dmi_processor_family(uint8_t code, char *manufacturer)
 	"Dual-Core Xeon 7100",
 	"Quad-Core Xeon 5400",
 	"Quad-Core Xeon",	/* 0xAA */
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-	NULL,			/* 0xAF */
+	"Dual-Core Xeon 5200",
+	"Dual-Core Xeon 7200",
+	"Quad-Core Xeon 7300",
+	"Quad-Core Xeon 7400",
+	"Multi-Core Xeon 7400",			/* 0xAF */
 	"Pentium III Xeon",
 	"Pentium III Speedstep",
 	"Pentium 4",
@@ -248,8 +249,8 @@ const char *dmi_processor_family(uint8_t code, char *manufacturer)
 	"Core 2 Extreme Mobile",
 	"Core 2 Duo Mobile",
 	"Core 2 Solo Mobile",
-	NULL,
-	NULL,			/* 0xC7 */
+	"Core i7",
+	"Dual-Core Celeron",		/* 0xC7 */
 	"IBM390",
 	"G4",
 	"G5",
@@ -264,16 +265,16 @@ const char *dmi_processor_family(uint8_t code, char *manufacturer)
 	"C7-D",
 	"C7",
 	"Eden",
-	NULL,			/*0xD6 */
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-	NULL,
+	"Multi-Core Xeon",			/*0xD6 */
+	"Dual-Core Xeon 3xxx",
+	"Quad-Core Xeon 3xxx",  /*0xD8 */
 	NULL,
+	"Dual-Core Xeon 5xxx", /*0xDA */
+	"Quad-Core Xeon 5xxx",
 	NULL,
+	"Dual-Core Xeon 7xxx", /*0xDD */
+	"Quad-Core Xeon 7xxx",
+	"Multi-Core Xeon 7xxx",
 	NULL,			/*0xE0 */
 	NULL,
 	NULL,
@@ -373,9 +374,10 @@ const char *dmi_processor_upgrade(uint8_t code)
 	"Socket S1",
 	"Socket AM2",
 	"Socket F (1207)"
+	"Socket LGA1366"	/* 0x19 */
     };
 
-    if (code >= 0x01 && code <= 0x18)
+    if (code >= 0x01 && code <= 0x19)
 	return upgrade[code - 0x01];
     return out_of_spec;
 }