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authorErwan Velu <erwan.velu@free.fr>2009-11-27 20:11:34 +0100
committerErwan Velu <erwan.velu@free.fr>2009-12-04 10:11:14 +0100
commit2b2af1e55e9adf673c4bfeb7f8a2e4a970703c20 (patch)
tree37673f54b2f1494afa4af490926226bd614207c7
parent86f0a14f7c045776b14c5ad8f7c4974f9e0cfc01 (diff)
downloadsyslinux-2b2af1e55e9adf673c4bfeb7f8a2e4a970703c20.tar.gz
hdt: Adding cpu cache management
Impact: Adding cpu cache CPU cache is now visible from HDT
-rw-r--r--com32/hdt/hdt-cli-cpu.c24
-rw-r--r--com32/hdt/hdt-menu-processor.c17
-rw-r--r--com32/hdt/hdt-menu-summary.c17
3 files changed, 50 insertions, 8 deletions
diff --git a/com32/hdt/hdt-cli-cpu.c b/com32/hdt/hdt-cli-cpu.c
index d4c9fba2..61b733d6 100644
--- a/com32/hdt/hdt-cli-cpu.c
+++ b/com32/hdt/hdt-cli-cpu.c
@@ -44,17 +44,21 @@ void main_show_cpu(int argc __unused, char **argv __unused,
more_printf(" Manufacturer : %s \n", hardware->cpu.vendor);
more_printf(" Product : %s \n", del_multi_spaces(hardware->cpu.model));
more_printf(" Number Cores : %d \n", hardware->cpu.num_cores);
+ more_printf(" L2 Cache : %dK\n", hardware->cpu.l2_cache_size);
- memset(features,0,sizeof(features));
- snprintf(features, sizeof(features)," Features : %d Mhz : ",hardware->dmi.processor.current_speed);
- if (hardware->cpu.flags.lm)
- strcat(features,"x86_64 64bit ");
+ memset(features, 0, sizeof(features));
+ snprintf(features, sizeof(features), " Features : %d Mhz : ",
+ hardware->dmi.processor.current_speed);
+ if (hardware->cpu.flags.lm)
+ strcat(features, "x86_64 64bit ");
else
- strcat(features,"x86 32bit ");
- if (hardware->cpu.flags.smp) strcat(features,"SMP ");
- if (hardware->cpu.flags.vmx || hardware->cpu.flags.svm) strcat(features,"HwVIRT ");
+ strcat(features, "x86 32bit ");
+ if (hardware->cpu.flags.smp)
+ strcat(features, "SMP ");
+ if (hardware->cpu.flags.vmx || hardware->cpu.flags.svm)
+ strcat(features, "HwVIRT ");
- more_printf("%s\n",features);
+ more_printf("%s\n", features);
}
static void show_flag(char *buffer, bool flag, char *flag_name, bool flush)
@@ -81,6 +85,10 @@ static void show_cpu(int argc __unused, char **argv __unused,
more_printf("Vendor : %s\n", hardware->cpu.vendor);
more_printf("Model : %s\n", hardware->cpu.model);
more_printf("Num. Cores: %d\n", hardware->cpu.num_cores);
+ more_printf("L1 Cache : %dK + %dK (I + D) \n",
+ hardware->cpu.l1_instruction_cache_size,
+ hardware->cpu.l1_data_cache_size);
+ more_printf("L2 Cache : %dK\n", hardware->cpu.l2_cache_size);
more_printf("Vendor ID : %d\n", hardware->cpu.vendor_id);
more_printf("Family ID : %d\n", hardware->cpu.family);
more_printf("Model ID : %d\n", hardware->cpu.model_id);
diff --git a/com32/hdt/hdt-menu-processor.c b/com32/hdt/hdt-menu-processor.c
index a538e4d4..4f7ac807 100644
--- a/com32/hdt/hdt-menu-processor.c
+++ b/com32/hdt/hdt-menu-processor.c
@@ -76,6 +76,23 @@ void compute_processor(struct s_my_menu *menu, struct s_hardware *hardware)
add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
menu->items_count++;
+ snprintf(buffer, sizeof buffer, "L1 Cache : %dK + %dK (I+D)",
+ hardware->cpu.l1_instruction_cache_size,
+ hardware->cpu.l1_data_cache_size);
+ snprintf(statbuffer, sizeof statbuffer,
+ "L1 Cache Size: %dK + %dK (Instruction + Data)",
+ hardware->cpu.l1_instruction_cache_size,
+ hardware->cpu.l1_data_cache_size);
+ add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
+ menu->items_count++;
+
+ snprintf(buffer, sizeof buffer, "L2 Cache : %dK",
+ hardware->cpu.l2_cache_size);
+ snprintf(statbuffer, sizeof statbuffer, "L2 Cache Size: %dK",
+ hardware->cpu.l2_cache_size);
+ add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
+ menu->items_count++;
+
snprintf(buffer, sizeof buffer, "Vendor ID : %d", hardware->cpu.vendor_id);
snprintf(statbuffer, sizeof statbuffer, "Vendor ID: %d",
hardware->cpu.vendor_id);
diff --git a/com32/hdt/hdt-menu-summary.c b/com32/hdt/hdt-menu-summary.c
index 53eaf61a..e9d56caf 100644
--- a/com32/hdt/hdt-menu-summary.c
+++ b/com32/hdt/hdt-menu-summary.c
@@ -51,6 +51,23 @@ void compute_summarymenu(struct s_my_menu *menu, struct s_hardware *hardware)
add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
menu->items_count++;
+ char features[SUBMENULEN + 1];
+ memset(features, 0, sizeof(features));
+ sprintf(features, "%d cores, %dK L2 Cache", hardware->cpu.num_cores,
+ hardware->cpu.l2_cache_size);
+ if (hardware->cpu.flags.lm)
+ strcat(features, ", 64bit");
+ else
+ strcat(features, ", 32bit");
+ if (hardware->cpu.flags.smp)
+ strcat(features, ", SMP ");
+ if (hardware->cpu.flags.vmx || hardware->cpu.flags.svm)
+ strcat(features, ", HwVIRT ");
+ snprintf(buffer, sizeof buffer, "%s", features);
+ snprintf(statbuffer, sizeof statbuffer, "Features : %s", features);
+ add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
+ menu->items_count++;
+
add_item("", "", OPT_SEP, "", 0);
if (hardware->is_dmi_valid == true) {