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// MIR for `unchecked_shr_signed_smaller` after PreCodegen
fn unchecked_shr_signed_smaller(_1: i16, _2: u32) -> i16 {
debug a => _1; // in scope 0 at $DIR/unchecked_shifts.rs:+0:44: +0:45
debug b => _2; // in scope 0 at $DIR/unchecked_shifts.rs:+0:52: +0:53
let mut _0: i16; // return place in scope 0 at $DIR/unchecked_shifts.rs:+0:63: +0:66
scope 1 (inlined core::num::<impl i16>::unchecked_shr) { // at $DIR/unchecked_shifts.rs:17:7: 17:23
debug self => _1; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
debug rhs => _2; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
let mut _3: i16; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
let mut _4: (u32,); // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
scope 2 {
}
}
bb0: {
StorageLive(_3); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
StorageLive(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
_4 = (_2,); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
_3 = core::num::<impl i16>::unchecked_shr::conv(move (_4.0: u32)) -> bb1; // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
// mir::Constant
// + span: $SRC_DIR/core/src/num/mod.rs:LL:COL
// + literal: Const { ty: fn(u32) -> i16 {core::num::<impl i16>::unchecked_shr::conv}, val: Value(<ZST>) }
}
bb1: {
StorageDead(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
_0 = unchecked_shr::<i16>(_1, move _3) -> [return: bb2, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
// mir::Constant
// + span: $SRC_DIR/core/src/num/int_macros.rs:LL:COL
// + literal: Const { ty: unsafe extern "rust-intrinsic" fn(i16, i16) -> i16 {unchecked_shr::<i16>}, val: Value(<ZST>) }
}
bb2: {
StorageDead(_3); // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
return; // scope 0 at $DIR/unchecked_shifts.rs:+2:2: +2:2
}
}
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