diff options
Diffstat (limited to 'chromium/v8/src/compiler/backend/instruction-codes.h')
| -rw-r--r-- | chromium/v8/src/compiler/backend/instruction-codes.h | 181 |
1 files changed, 126 insertions, 55 deletions
diff --git a/chromium/v8/src/compiler/backend/instruction-codes.h b/chromium/v8/src/compiler/backend/instruction-codes.h index 31d669813e2..56d4d960bd3 100644 --- a/chromium/v8/src/compiler/backend/instruction-codes.h +++ b/chromium/v8/src/compiler/backend/instruction-codes.h @@ -17,6 +17,8 @@ #include "src/compiler/backend/mips/instruction-codes-mips.h" #elif V8_TARGET_ARCH_MIPS64 #include "src/compiler/backend/mips64/instruction-codes-mips64.h" +#elif V8_TARGET_ARCH_LOONG64 +#include "src/compiler/backend/loong64/instruction-codes-loong64.h" #elif V8_TARGET_ARCH_X64 #include "src/compiler/backend/x64/instruction-codes-x64.h" #elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64 @@ -30,6 +32,7 @@ #define TARGET_ADDRESSING_MODE_LIST(V) #endif #include "src/base/bit-field.h" +#include "src/codegen/atomic-memory-order.h" #include "src/compiler/write-barrier-kind.h" namespace v8 { @@ -89,7 +92,7 @@ inline RecordWriteMode WriteBarrierKindToRecordWriteMode( V(ArchBinarySearchSwitch) \ V(ArchTableSwitch) \ V(ArchNop) \ - V(ArchAbortCSAAssert) \ + V(ArchAbortCSADcheck) \ V(ArchDebugBreak) \ V(ArchComment) \ V(ArchThrowTerminator) \ @@ -99,53 +102,53 @@ inline RecordWriteMode WriteBarrierKindToRecordWriteMode( V(ArchParentFramePointer) \ V(ArchTruncateDoubleToI) \ V(ArchStoreWithWriteBarrier) \ + V(ArchAtomicStoreWithWriteBarrier) \ V(ArchStackSlot) \ - V(ArchWordPoisonOnSpeculation) \ V(ArchStackPointerGreaterThan) \ V(ArchStackCheckOffset) \ - V(Word32AtomicLoadInt8) \ - V(Word32AtomicLoadUint8) \ - V(Word32AtomicLoadInt16) \ - V(Word32AtomicLoadUint16) \ - V(Word32AtomicLoadWord32) \ - V(Word32AtomicStoreWord8) \ - V(Word32AtomicStoreWord16) \ - V(Word32AtomicStoreWord32) \ - V(Word32AtomicExchangeInt8) \ - V(Word32AtomicExchangeUint8) \ - V(Word32AtomicExchangeInt16) \ - V(Word32AtomicExchangeUint16) \ - V(Word32AtomicExchangeWord32) \ - V(Word32AtomicCompareExchangeInt8) \ - V(Word32AtomicCompareExchangeUint8) \ - V(Word32AtomicCompareExchangeInt16) \ - V(Word32AtomicCompareExchangeUint16) \ - V(Word32AtomicCompareExchangeWord32) \ - V(Word32AtomicAddInt8) \ - V(Word32AtomicAddUint8) \ - V(Word32AtomicAddInt16) \ - V(Word32AtomicAddUint16) \ - V(Word32AtomicAddWord32) \ - V(Word32AtomicSubInt8) \ - V(Word32AtomicSubUint8) \ - V(Word32AtomicSubInt16) \ - V(Word32AtomicSubUint16) \ - V(Word32AtomicSubWord32) \ - V(Word32AtomicAndInt8) \ - V(Word32AtomicAndUint8) \ - V(Word32AtomicAndInt16) \ - V(Word32AtomicAndUint16) \ - V(Word32AtomicAndWord32) \ - V(Word32AtomicOrInt8) \ - V(Word32AtomicOrUint8) \ - V(Word32AtomicOrInt16) \ - V(Word32AtomicOrUint16) \ - V(Word32AtomicOrWord32) \ - V(Word32AtomicXorInt8) \ - V(Word32AtomicXorUint8) \ - V(Word32AtomicXorInt16) \ - V(Word32AtomicXorUint16) \ - V(Word32AtomicXorWord32) \ + V(AtomicLoadInt8) \ + V(AtomicLoadUint8) \ + V(AtomicLoadInt16) \ + V(AtomicLoadUint16) \ + V(AtomicLoadWord32) \ + V(AtomicStoreWord8) \ + V(AtomicStoreWord16) \ + V(AtomicStoreWord32) \ + V(AtomicExchangeInt8) \ + V(AtomicExchangeUint8) \ + V(AtomicExchangeInt16) \ + V(AtomicExchangeUint16) \ + V(AtomicExchangeWord32) \ + V(AtomicCompareExchangeInt8) \ + V(AtomicCompareExchangeUint8) \ + V(AtomicCompareExchangeInt16) \ + V(AtomicCompareExchangeUint16) \ + V(AtomicCompareExchangeWord32) \ + V(AtomicAddInt8) \ + V(AtomicAddUint8) \ + V(AtomicAddInt16) \ + V(AtomicAddUint16) \ + V(AtomicAddWord32) \ + V(AtomicSubInt8) \ + V(AtomicSubUint8) \ + V(AtomicSubInt16) \ + V(AtomicSubUint16) \ + V(AtomicSubWord32) \ + V(AtomicAndInt8) \ + V(AtomicAndUint8) \ + V(AtomicAndInt16) \ + V(AtomicAndUint16) \ + V(AtomicAndWord32) \ + V(AtomicOrInt8) \ + V(AtomicOrUint8) \ + V(AtomicOrInt16) \ + V(AtomicOrUint16) \ + V(AtomicOrWord32) \ + V(AtomicXorInt8) \ + V(AtomicXorUint8) \ + V(AtomicXorInt16) \ + V(AtomicXorUint16) \ + V(AtomicXorWord32) \ V(Ieee754Float64Acos) \ V(Ieee754Float64Acosh) \ V(Ieee754Float64Asin) \ @@ -208,12 +211,10 @@ V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os, enum FlagsMode { kFlags_none = 0, kFlags_branch = 1, - kFlags_branch_and_poison = 2, - kFlags_deoptimize = 3, - kFlags_deoptimize_and_poison = 4, - kFlags_set = 5, - kFlags_trap = 6, - kFlags_select = 7, + kFlags_deoptimize = 2, + kFlags_set = 3, + kFlags_trap = 4, + kFlags_select = 5, }; V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os, @@ -262,9 +263,20 @@ V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os, enum MemoryAccessMode { kMemoryAccessDirect = 0, kMemoryAccessProtected = 1, - kMemoryAccessPoisoned = 2 }; +enum class AtomicWidth { kWord32, kWord64 }; + +inline size_t AtomicWidthSize(AtomicWidth width) { + switch (width) { + case AtomicWidth::kWord32: + return 4; + case AtomicWidth::kWord64: + return 8; + } + UNREACHABLE(); +} + // The InstructionCode is an opaque, target-specific integer that encodes // what code to emit for an instruction in the code generator. It is not // interesting to the register allocator, as the inputs and flags on the @@ -279,15 +291,74 @@ using ArchOpcodeField = base::BitField<ArchOpcode, 0, 9>; static_assert(ArchOpcodeField::is_valid(kLastArchOpcode), "All opcodes must fit in the 9-bit ArchOpcodeField."); using AddressingModeField = base::BitField<AddressingMode, 9, 5>; +static_assert( + AddressingModeField::is_valid(kLastAddressingMode), + "All addressing modes must fit in the 5-bit AddressingModeField."); using FlagsModeField = base::BitField<FlagsMode, 14, 3>; using FlagsConditionField = base::BitField<FlagsCondition, 17, 5>; -using DeoptImmedArgsCountField = base::BitField<int, 22, 2>; -using DeoptFrameStateOffsetField = base::BitField<int, 24, 8>; +using MiscField = base::BitField<int, 22, 10>; + +// {MiscField} is used for a variety of things, depending on the opcode. +// TODO(turbofan): There should be an abstraction that ensures safe encoding and +// decoding. {HasMemoryAccessMode} and its uses are a small step in that +// direction. + // LaneSizeField and AccessModeField are helper types to encode/decode a lane // size, an access mode, or both inside the overlapping MiscField. using LaneSizeField = base::BitField<int, 22, 8>; using AccessModeField = base::BitField<MemoryAccessMode, 30, 2>; -using MiscField = base::BitField<int, 22, 10>; +// TODO(turbofan): {HasMemoryAccessMode} is currently only used to guard +// decoding (in CodeGenerator and InstructionScheduler). Encoding (in +// InstructionSelector) is not yet guarded. There are in fact instructions for +// which InstructionSelector does set a MemoryAccessMode but CodeGenerator +// doesn't care to consume it (e.g. kArm64LdrDecompressTaggedSigned). This is +// scary. {HasMemoryAccessMode} does not include these instructions, so they can +// be easily found by guarding encoding. +inline bool HasMemoryAccessMode(ArchOpcode opcode) { + switch (opcode) { +#define CASE(Name) \ + case k##Name: \ + return true; + TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(CASE) +#undef CASE + default: + return false; + } +} + +using DeoptImmedArgsCountField = base::BitField<int, 22, 2>; +using DeoptFrameStateOffsetField = base::BitField<int, 24, 8>; + +// AtomicWidthField overlaps with MiscField and is used for the various Atomic +// opcodes. Only used on 64bit architectures. All atomic instructions on 32bit +// architectures are assumed to be 32bit wide. +using AtomicWidthField = base::BitField<AtomicWidth, 22, 2>; + +// AtomicMemoryOrderField overlaps with MiscField and is used for the various +// Atomic opcodes. This field is not used on all architectures. It is used on +// architectures where the codegen for kSeqCst and kAcqRel differ only by +// emitting fences. +using AtomicMemoryOrderField = base::BitField<AtomicMemoryOrder, 24, 2>; +using AtomicStoreRecordWriteModeField = base::BitField<RecordWriteMode, 26, 4>; + +// ParamField and FPParamField overlap with MiscField, as the latter is never +// used for Call instructions. These 2 fields represent the general purpose +// and floating point parameter counts of a direct call into C and are given 5 +// bits each, which allow storing a number up to the current maximum parameter +// count, which is 20 (see kMaxCParameters defined in macro-assembler.h). +using ParamField = base::BitField<int, 22, 5>; +using FPParamField = base::BitField<int, 27, 5>; + +// This static assertion serves as an early warning if we are about to exhaust +// the available opcode space. If we are about to exhaust it, we should start +// looking into options to compress some opcodes (see +// https://crbug.com/v8/12093) before we fully run out of available opcodes. +// Otherwise we risk being unable to land an important security fix or merge +// back fixes that add new opcodes. +// It is OK to temporarily reduce the required slack if we have a tracking bug +// to reduce the number of used opcodes again. +static_assert(ArchOpcodeField::kMax - kLastArchOpcode >= 16, + "We are running close to the number of available opcodes."); } // namespace compiler } // namespace internal |