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* target/s390x: Fix EXECUTE of relative branchesIlya Leoshkevich2023-05-161-23/+58
* s390x/tcg: Fix LDER instruction formatIlya Leoshkevich2023-05-161-1/+1
* hw/core: Use a callback for target specific query-cpus-fast informationThomas Huth2023-05-161-0/+8
* Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu i...Richard Henderson2023-05-134-53/+81
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| * target/openrisc: Setup FPU for detecting tininess before roundingStafford Horne2023-05-111-0/+4
| * target/openrisc: Set PC to cpu state on FPU exceptionStafford Horne2023-05-111-2/+11
| * target/openrisc: Allow fpcsr access in user modeStafford Horne2023-05-112-51/+66
* | target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size checkPeter Maydell2023-05-125-19/+30
* | target/arm: Select CONFIG_ARM_V7M when TCG is enabledFabiano Rosas2023-05-121-0/+1
* | target/arm: Select SEMIHOSTING when using TCGFabiano Rosas2023-05-121-7/+1
* | target/arm: Fix handling of SW and NSW bits for stage 2 walksPeter Maydell2023-05-121-25/+51
* | target/arm: Don't allow stage 2 page table walks to downgrade to NSPeter Maydell2023-05-121-2/+3
* | target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/Richard Henderson2023-05-125-4/+4
* | target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/Richard Henderson2023-05-123-0/+0
* | target/loongarch: Do not include tcg-ldst.hRichard Henderson2023-05-112-2/+0
* | target/sh4: Use MO_ALIGN where requiredRichard Henderson2023-05-111-36/+66
* | target/nios2: Remove TARGET_ALIGNED_ONLYRichard Henderson2023-05-111-0/+10
* | target/mips: Use MO_ALIGN instead of 0Richard Henderson2023-05-111-1/+1
* | target/mips: Add missing default_tcg_memop_maskRichard Henderson2023-05-114-28/+42
* | target/mips: Add MO_ALIGN to gen_llwp, gen_scwpRichard Henderson2023-05-111-2/+3
* | target/m68k: Fix gen_load_fp for OS_LONGRichard Henderson2023-05-111-0/+1
* | target/loongarch: Terminate vmstate subsections listRichard Henderson2023-05-101-0/+1
* | target/i386: Add EPYC-Genoa model to support Zen 4 processor seriesBabu Moger2023-05-081-0/+122
* | target/i386: Add VNMI and automatic IBRS feature bitsBabu Moger2023-05-082-2/+5
* | target/i386: Add missing feature bits in EPYC-Milan modelBabu Moger2023-05-081-0/+70
* | target/i386: Add feature bits for CPUID_Fn80000021_EAXBabu Moger2023-05-082-0/+32
* | target/i386: Add a couple of feature bits in 8000_0008_EBXBabu Moger2023-05-082-2/+6
* | target/i386: Add new EPYC CPU versions with updated cache_infoMichael Roth2023-05-081-0/+118
* | target/i386: allow versioned CPUs to specify new cache_infoMichael Roth2023-05-081-3/+32
* | Merge tag 'pull-loongarch-20230506' of https://gitlab.com/gaosong/qemu into s...Richard Henderson2023-05-0618-55/+9986
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| * | target/loongarch: CPUCFG support LSXSong Gao2023-05-061-0/+1
| * | target/loongarch: Use {set/get}_gpr replace to cpu_fprSong Gao2023-05-065-43/+129
| * | target/loongarch: Implement vldiSong Gao2023-05-063-0/+148
| * | target/loongarch: Implement vld vstSong Gao2023-05-064-0/+239
| * | target/loongarch: Implement vilvl vilvh vextrins vshufSong Gao2023-05-065-0/+248
| * | target/loongarch: Implement vreplve vpack vpickSong Gao2023-05-065-0/+319
| * | target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vrSong Gao2023-05-063-0/+173
| * | target/loongarch: Implement vbitsel vsetSong Gao2023-05-065-0/+174
| * | target/loongarch: Implement vfcmpSong Gao2023-05-065-0/+190
| * | target/loongarch: Implement vseq vsle vsltSong Gao2023-05-065-0/+332
| * | target/loongarch: Implement LSX fpu fcvt instructionsSong Gao2023-05-065-0/+600
| * | target/loongarch: Implement LSX fpu arith instructionsSong Gao2023-05-068-1/+377
| * | target/loongarch: Implement vfrstpSong Gao2023-05-065-0/+61
| * | target/loongarch: Implement vbitclr vbitset vbitrevSong Gao2023-05-065-0/+437
| * | target/loongarch: Implement vpcntSong Gao2023-05-065-0/+38
| * | target/loongarch: Implement vclo vclzSong Gao2023-05-065-0/+67
| * | target/loongarch: Implement vssrlrn vssrarnSong Gao2023-05-065-0/+478
| * | target/loongarch: Implement vssrln vssranSong Gao2023-05-065-0/+499
| * | target/loongarch: Implement vsrlrn vsrarnSong Gao2023-05-065-0/+190
| * | target/loongarch: Implement vsrln vsranSong Gao2023-05-065-0/+179
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