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authorRichard Henderson <richard.henderson@linaro.org>2023-04-19 11:50:36 +0200
committerRichard Henderson <richard.henderson@linaro.org>2023-05-16 16:30:29 -0700
commit37e523f04b09f2e653629ac16206512d8a5ebc85 (patch)
tree82dc7fbd5942c2cff541ec913033a27052d2c81a
parent1bac4697199dd9aa5d8d0e3c56d0ea52b2bd0fa1 (diff)
downloadqemu-37e523f04b09f2e653629ac16206512d8a5ebc85.tar.gz
tcg/riscv: Use atom_and_align_for_opc
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--tcg/riscv/tcg-target.c.inc13
1 files changed, 8 insertions, 5 deletions
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 37870c89fc..1fc1a9199b 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -910,8 +910,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
{
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
- unsigned a_bits = get_alignment_bits(opc);
- unsigned a_mask = (1u << a_bits) - 1;
+ TCGAtomAlign aa;
+ unsigned a_mask;
+
+ aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
+ a_mask = (1u << aa.align) - 1;
#ifdef CONFIG_SOFTMMU
unsigned s_bits = opc & MO_SIZE;
@@ -944,7 +947,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
* cross pages using the address of the last byte of the access.
*/
addr_adj = addr_reg;
- if (a_bits < s_bits) {
+ if (a_mask < s_mask) {
addr_adj = TCG_REG_TMP0;
tcg_out_opc_imm(s, TARGET_LONG_BITS == 32 ? OPC_ADDIW : OPC_ADDI,
addr_adj, addr_reg, s_mask - a_mask);
@@ -983,8 +986,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
ldst->oi = oi;
ldst->addrlo_reg = addr_reg;
- /* We are expecting a_bits max 7, so we can always use andi. */
- tcg_debug_assert(a_bits < 12);
+ /* We are expecting alignment max 7, so we can always use andi. */
+ tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12));
tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask);
ldst->label_ptr[0] = s->code_ptr;