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authorRichard Henderson <rth@twiddle.net>2011-05-02 08:48:14 -0700
committerRichard Henderson <rth@twiddle.net>2011-05-02 10:16:53 -0700
commit2441ea1234e5b4399954ca64a101794cf6e813b3 (patch)
tree44132ef73b15e4929cad97bde91729fe4142f9f1
parent28a139998d9c6f123168c0edd5117ab00c0a6288 (diff)
downloadqemu-palcode-2441ea1234e5b4399954ca64a101794cf6e813b3.tar.gz
clipper: Report ISA interrupts properly.
-rw-r--r--core-typhoon.h28
-rw-r--r--pal.S7
-rw-r--r--sys-clipper.S40
3 files changed, 56 insertions, 19 deletions
diff --git a/core-typhoon.h b/core-typhoon.h
index 854d4d0..cee6e95 100644
--- a/core-typhoon.h
+++ b/core-typhoon.h
@@ -105,6 +105,7 @@
#define TYPHOON_PCHIP0_PCI_MEM 0
#define TYPHOON_PCHIP0_PCI_IO 0x1fc000000
#define TYPHOON_PCHIP0_PCI_CONF 0x1fe000000
+#define TYPHOON_PCHIP0_PCI_IACK 0x1f8000000
#ifdef __ASSEMBLER__
@@ -117,18 +118,28 @@
64-bit constants, dropping them all into the .lit8 section. It is
better for us to build these by hand. */
.macro LOAD_PHYS_CCHIP ret
- lda \ret, 0x400d
+ lda \ret, (PIO_PHYS_ADDR + TYPHOON_CCHIP) >> 29
sll \ret, 29, \ret
.endm
.macro LOAD_PHYS_PCHIP0 ret
- lda \ret, 0x400c
+ lda \ret, (PIO_PHYS_ADDR + TYPHOON_PCHIP0) >> 29
sll \ret, 29, \ret
.endm
+.macro LOAD_PHYS_PCHIP0_IACK ret
+ .set macro
+ lda \ret, (PIO_PHYS_ADDR + TYPHOON_PCHIP0_PCI_IACK) >> 24
+ .set nomacro
+ sll \ret, 24, \ret
+.endm
+
.macro LOAD_KSEG_PCI_IO ret
- ldah \ret, -48
- lda \ret, 0x1fc0(\ret)
+ .set macro
+ // Note that GAS shifts are logical. Force arithmetic shift style
+ // results by negating before and after the shift.
+ lda \ret, -(-(PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_IO) >> 20)
+ .set nomacro
sll \ret, 20, \ret
.endm
@@ -160,15 +171,6 @@
stq_p \t2, TYPHOON_CCHIP_MISC(\t0)
.endm
-/* Load the device interrupt vector. */
-.macro SYS_DEV_VECTOR ret
- mfpr \ret, ptCpuDIR
- ldq_p \ret, 0(\ret)
- cttz \ret, \ret
- sll \ret, 4, \ret
- lda \ret, 0x800(\ret)
-.endm
-
/* Interrupt another CPU. */
.macro SYS_WRIPIR target, t0, t1, t2
LOAD_PHYS_CCHIP \t0
diff --git a/pal.S b/pal.S
index 2bc0b9c..1d579aa 100644
--- a/pal.S
+++ b/pal.S
@@ -212,14 +212,12 @@ Pal_Dev_Interrupt:
mov IPL_K_DEV1, p0 // Raise IPL
mtpr p0, qemu_ps
+ bsr p7, Sys_Dev_Vector
+
mfpr p7, ptEntInt
mfpr $gp, ptKgp
-
lda a0, INT_K_DEV
lda a2, 0
-
- SYS_DEV_VECTOR a1
-
hw_ret (p7)
ENDFN Pal_Dev_Interrupt
@@ -1251,6 +1249,7 @@ ENDFN CallPal_WtInt
* r18 (a2) <- (sp+40)
*/
ORG_CALL_PAL_PRIV(0x3F)
+ .globl CallPal_Rti
CallPal_Rti:
mfpr p6, qemu_exc_addr // Save exc_addr for machine check
diff --git a/sys-clipper.S b/sys-clipper.S
index 5296c91..a5771fa 100644
--- a/sys-clipper.S
+++ b/sys-clipper.S
@@ -28,8 +28,8 @@
*
* INPUT PARAMETERS
*
- * r16 (a0) = whami
- * r26 (ra) = return address
+ * a0 = whami
+ * p7 = return address
*/
.globl Sys_Setup
.ent Sys_Setup
@@ -55,6 +55,42 @@ Sys_Setup:
.end Sys_Setup
/*
+ * Sys_Dev_Vector
+ *
+ * Load the SRM interrupt vector for the system.
+ *
+ * INPUT PARAMETERS
+ *
+ * p7 = return address
+ *
+ * OUTPUT PARAMETERS
+ *
+ * a1 = interrupt vector
+ */
+
+ .globl Sys_Dev_Vector
+ .ent Sys_Dev_Vector
+Sys_Dev_Vector:
+ .frame $sp, 0, p7, 0
+ mfpr a1, ptCpuDIR // Load int mask for this CPU
+ ldq_p a1, 0(a1)
+ beq a1, CallPal_Rti // No interrupts asserted?
+
+ cttz a1, a1 // Find the first asserted interrupt.
+
+ cmpeq a1, 55, a0 // Is this an ISA interrupt?
+ addq a1, 16, a1 // PCI interrupt numbers start at 16
+ beq a0, 1f
+
+ LOAD_PHYS_PCHIP0_IACK a1 // IACK results in the ISA irq
+ ldl_p a1, 0(a1)
+
+1: sll a1, 4, a1
+ lda a1, 0x800(a1)
+ ret $31, (p7), 0
+ .end Sys_Dev_Vector
+
+/*
* Cserve_Ena
*
* Unmask a PCI interrupt