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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2021-09-02 10:06:02 +0100 |
|---|---|---|
| committer | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2021-09-02 10:17:46 +0100 |
| commit | d657b653186c0fd6e062cab133497415c2a5a5b8 (patch) | |
| tree | 9c89a293353aec1a4de26ba22a7c409e676bae5d | |
| parent | 9cd695aa3ca280ecc0b867be59d45d0605caf12b (diff) | |
| download | qemu-openbios-d657b653186c0fd6e062cab133497415c2a5a5b8.tar.gz | |
escc: send software reset command before configuring the port
According to the ESCC datasheet all register values are undetermined until an
explicit reset command is sent. This is required to fix an issue with QEMU's
ESCC device to ensure that the registers are set to default values if the
default power-on values are changed.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
| -rw-r--r-- | drivers/escc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/escc.c b/drivers/escc.c index 4da89174..0f0d43a3 100644 --- a/drivers/escc.c +++ b/drivers/escc.c @@ -46,6 +46,9 @@ static volatile unsigned char *escc_serial_dev; #define Tx8 0x60 /* Tx 8 bits/character */ #define DTR 0x80 /* DTR */ +/* Write Register 9 */ +#define SW_CHAN_RESET_B 0x40 /* Software reset channel B */ + /* Write Register 14 (Misc control bits) */ #define BRENAB 1 /* Baud rate generator enable */ #define BRSRC 2 /* Baud rate generator source */ @@ -80,6 +83,9 @@ static void escc_uart_port_putchar(uintptr_t port, unsigned char c) static void uart_init_line(volatile unsigned char *port, unsigned long baud, int index) { + CTRL(port) = 9; // reg 9 + CTRL(port) = SW_CHAN_RESET_B << index; + CTRL(port) = 4; // reg 4 CTRL(port) = SB1 | X16CLK; // no parity, async, 1 stop bit, 16x // clock |