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| author | Guillaume Emont <guijemont@igalia.com> | 2012-12-13 17:46:59 +0100 |
|---|---|---|
| committer | Guillaume Emont <guijemont@igalia.com> | 2012-12-28 15:23:38 +0100 |
| commit | 5ff42a85f583f872433550aedea8e527a3e896d1 (patch) | |
| tree | 65f61937b526727f4023778312dd3e1d9837735d | |
| parent | 17141dfe3ab4f2b87f1087b59124b7038bd933fe (diff) | |
| download | orc-5ff42a85f583f872433550aedea8e527a3e896d1.tar.gz | |
mips: convsbw: spread bytes when we have an instruction shift
| -rw-r--r-- | orc/orcrules-mips.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/orc/orcrules-mips.c b/orc/orcrules-mips.c index 65ec982..143b23d 100644 --- a/orc/orcrules-mips.c +++ b/orc/orcrules-mips.c @@ -281,8 +281,14 @@ mips_rule_convsbw (OrcCompiler *compiler, void *user, OrcInstruction *insn) /* left shift 8 bits, then right shift signed 8 bits, so that the sign bit * gets replicated in the upper 8 bits */ - orc_mips_emit_shll_ph (compiler, dest, src, 8); - orc_mips_emit_shra_ph (compiler, dest, dest, 8); + if (compiler->insn_shift > 0) { + orc_mips_emit_preceu_ph_qbr (compiler, dest, src); + orc_mips_emit_shll_ph (compiler, dest, dest, 8); + orc_mips_emit_shra_ph (compiler, dest, dest, 8); + } else { + orc_mips_emit_shll_ph (compiler, dest, src, 8); + orc_mips_emit_shra_ph (compiler, dest, dest, 8); + } } void |