diff options
| author | Andy Polyakov <appro@openssl.org> | 2018-02-11 12:29:06 +0100 |
|---|---|---|
| committer | Andy Polyakov <appro@openssl.org> | 2018-02-12 14:04:53 +0100 |
| commit | 77f3612e2bd930b27dcab63fdcca1d7091cb948d (patch) | |
| tree | 1bc8052e36ad1a604fa11da19409b117589ec661 /crypto | |
| parent | 1d0c08b4963f5f7e1d1855e360417a11973d8455 (diff) | |
| download | openssl-new-77f3612e2bd930b27dcab63fdcca1d7091cb948d.tar.gz | |
crypto/armcap.c: detect hardware-assisted SHA512 support.
Reviewed-by: Rich Salz <rsalz@openssl.org>
Diffstat (limited to 'crypto')
| -rwxr-xr-x | crypto/arm64cpuid.pl | 8 | ||||
| -rw-r--r-- | crypto/arm_arch.h | 1 | ||||
| -rw-r--r-- | crypto/armcap.c | 15 |
3 files changed, 24 insertions, 0 deletions
diff --git a/crypto/arm64cpuid.pl b/crypto/arm64cpuid.pl index caa33875c9..68734f5bed 100755 --- a/crypto/arm64cpuid.pl +++ b/crypto/arm64cpuid.pl @@ -63,6 +63,7 @@ _armv8_sha256_probe: sha256su0 v0.4s, v0.4s ret .size _armv8_sha256_probe,.-_armv8_sha256_probe + .globl _armv8_pmull_probe .type _armv8_pmull_probe,%function _armv8_pmull_probe: @@ -70,6 +71,13 @@ _armv8_pmull_probe: ret .size _armv8_pmull_probe,.-_armv8_pmull_probe +.globl _armv8_sha512_probe +.type _armv8_sha512_probe,%function +_armv8_sha512_probe: + .long 0xcec08000 // sha512su0 v0.2d,v0.2d + ret +.size _armv8_sha512_probe,.-_armv8_sha512_probe + .globl OPENSSL_cleanse .type OPENSSL_cleanse,%function .align 5 diff --git a/crypto/arm_arch.h b/crypto/arm_arch.h index 8b41408296..395ada61a4 100644 --- a/crypto/arm_arch.h +++ b/crypto/arm_arch.h @@ -79,5 +79,6 @@ extern unsigned int OPENSSL_armcap_P; # define ARMV8_SHA1 (1<<3) # define ARMV8_SHA256 (1<<4) # define ARMV8_PMULL (1<<5) +# define ARMV8_SHA512 (1<<6) #endif diff --git a/crypto/armcap.c b/crypto/armcap.c index a1f77fa2fc..deffd93cc6 100644 --- a/crypto/armcap.c +++ b/crypto/armcap.c @@ -46,6 +46,9 @@ void _armv8_aes_probe(void); void _armv8_sha1_probe(void); void _armv8_sha256_probe(void); void _armv8_pmull_probe(void); +# ifdef __aarch64__ +void _armv8_sha512_probe(void); +# endif uint32_t _armv7_tick(void); uint32_t OPENSSL_rdtsc(void) @@ -94,6 +97,7 @@ static unsigned long (*getauxval) (unsigned long) = NULL; # define HWCAP_CE_PMULL (1 << 4) # define HWCAP_CE_SHA1 (1 << 5) # define HWCAP_CE_SHA256 (1 << 6) +# define HWCAP_CE_SHA512 (1 << 21) # endif void OPENSSL_cpuid_setup(void) @@ -163,6 +167,11 @@ void OPENSSL_cpuid_setup(void) if (hwcap & HWCAP_CE_SHA256) OPENSSL_armcap_P |= ARMV8_SHA256; + +# ifdef __aarch64__ + if (hwcap & HWCAP_CE_SHA512) + OPENSSL_armcap_P |= ARMV8_SHA512; +# endif } } else if (sigsetjmp(ill_jmp, 1) == 0) { _armv7_neon_probe(); @@ -182,6 +191,12 @@ void OPENSSL_cpuid_setup(void) _armv8_sha256_probe(); OPENSSL_armcap_P |= ARMV8_SHA256; } +# ifdef __aarch64__ + if (sigsetjmp(ill_jmp, 1) == 0) { + _armv8_sha512_probe(); + OPENSSL_armcap_P |= ARMV8_SHA512; + } +# endif } if (sigsetjmp(ill_jmp, 1) == 0) { _armv7_tick(); |