diff options
| author | Andrey Matyukov <andrey.matyukov@intel.com> | 2020-12-08 22:53:39 +0300 |
|---|---|---|
| committer | Matt Caswell <matt@openssl.org> | 2021-03-22 09:48:00 +0000 |
| commit | c781eb1c63c243cb64dbe3066a43dc172aaab3b8 (patch) | |
| tree | 36adf4600064afddfb87e16bee0736c6427ca523 /crypto/x86_64cpuid.pl | |
| parent | db89d8f04bb131bbf0e2b87eb9a1515076c893d3 (diff) | |
| download | openssl-new-c781eb1c63c243cb64dbe3066a43dc172aaab3b8.tar.gz | |
Dual 1024-bit exponentiation optimization for Intel IceLake CPU
with AVX512_IFMA + AVX512_VL instructions, primarily for RSA CRT private key
operations. It uses 256-bit registers to avoid CPU frequency scaling issues.
The performance speedup for RSA2k signature on ICL is ~2x.
Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Matt Caswell <matt@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/13750)
Diffstat (limited to 'crypto/x86_64cpuid.pl')
| -rw-r--r-- | crypto/x86_64cpuid.pl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/crypto/x86_64cpuid.pl b/crypto/x86_64cpuid.pl index d3e2b9145a..9f7a1b092f 100644 --- a/crypto/x86_64cpuid.pl +++ b/crypto/x86_64cpuid.pl @@ -215,7 +215,7 @@ OPENSSL_ia32_cpuid: cmp \$0xe6,%eax je .Ldone andl \$0x3fdeffff,8(%rdi) # ~(1<<31|1<<30|1<<21|1<<16) - # clear AVX512F+BW+VL+FIMA, all of + # clear AVX512F+BW+VL+IFMA, all of # them are EVEX-encoded, which requires # ZMM state support even if one uses # only XMM and YMM :-( |