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| author | fangming.fang <fangming.fang@arm.com> | 2021-12-24 08:29:04 +0000 |
|---|---|---|
| committer | Tomas Mraz <tomas@openssl.org> | 2022-01-14 11:40:05 +0100 |
| commit | 71396cd048072b69559b46d98cfebfd4474cd712 (patch) | |
| tree | 3b29b3ce3f469473600816c6fdabf79e858ce91b /crypto/armcap.c | |
| parent | 79704a88eb5aa70fa506e3e59a29fcda21f428af (diff) | |
| download | openssl-new-71396cd048072b69559b46d98cfebfd4474cd712.tar.gz | |
SM3 acceleration with SM3 hardware instruction on aarch64
SM3 hardware instruction is optional feature of crypto extension for
aarch64. This implementation accelerates SM3 via SM3 instructions. For
the platform not supporting SM3 instruction, the original C
implementation still works. Thanks to AliBaba for testing and reporting
the following perf numbers for Yitian710:
Benchmark on T-Head Yitian-710 2.75GHz:
Before:
type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 16384 bytes
sm3 49297.82k 121062.63k 223106.05k 283371.52k 307574.10k 309400.92k
After (33% - 74% faster):
type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 16384 bytes
sm3 65640.01k 179121.79k 359854.59k 481448.96k 534055.59k 538274.47k
Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/17454)
Diffstat (limited to 'crypto/armcap.c')
| -rw-r--r-- | crypto/armcap.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/crypto/armcap.c b/crypto/armcap.c index 72ed0a024a..93003c9121 100644 --- a/crypto/armcap.c +++ b/crypto/armcap.c @@ -53,6 +53,7 @@ void _armv8_sha1_probe(void); void _armv8_sha256_probe(void); void _armv8_pmull_probe(void); # ifdef __aarch64__ +void _armv8_sm3_probe(void); void _armv8_sha512_probe(void); unsigned int _armv8_cpuid_probe(void); void _armv8_rng_probe(void); @@ -169,6 +170,7 @@ static unsigned long getauxval(unsigned long key) # define HWCAP_CE_SHA1 (1 << 5) # define HWCAP_CE_SHA256 (1 << 6) # define HWCAP_CPUID (1 << 11) +# define HWCAP_CE_SM3 (1 << 18) # define HWCAP_CE_SHA512 (1 << 21) /* AT_HWCAP2 */ # define HWCAP2 26 @@ -245,6 +247,9 @@ void OPENSSL_cpuid_setup(void) if (hwcap & HWCAP_CPUID) OPENSSL_armcap_P |= ARMV8_CPUID; + + if (hwcap & HWCAP_CE_SM3) + OPENSSL_armcap_P |= ARMV8_SM3; # endif } # ifdef __aarch64__ @@ -292,6 +297,11 @@ void OPENSSL_cpuid_setup(void) _armv8_sha512_probe(); OPENSSL_armcap_P |= ARMV8_SHA512; } + + if (sigsetjmp(ill_jmp, 1) == 0) { + _armv8_sm3_probe(); + OPENSSL_armcap_P |= ARMV8_SM3; + } # endif } # ifdef __aarch64__ |