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| author | Damien Doligez <damien.doligez-inria.fr> | 2010-05-21 12:00:49 +0000 |
|---|---|---|
| committer | Damien Doligez <damien.doligez-inria.fr> | 2010-05-21 12:00:49 +0000 |
| commit | 5e67123bf67b4a92307a4b3063fbc247306b7614 (patch) | |
| tree | 2cc00b80ff15a64bc268053bb1d55eb28d3fdc2b /asmcomp/schedgen.ml | |
| parent | d9d8ff4749fcddb5aa6e18e9e94ef64de8234cce (diff) | |
| download | ocaml-5e67123bf67b4a92307a4b3063fbc247306b7614.tar.gz | |
PR#4975: spelling mistakes "overriden" and "informations"
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@10450 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
Diffstat (limited to 'asmcomp/schedgen.ml')
| -rw-r--r-- | asmcomp/schedgen.ml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/asmcomp/schedgen.ml b/asmcomp/schedgen.ml index 388d0d4c8c..00762fa36a 100644 --- a/asmcomp/schedgen.ml +++ b/asmcomp/schedgen.ml @@ -115,7 +115,7 @@ let some_load = (Iload(Cmm.Word, Arch.identity_addressing)) class virtual scheduler_generic = object (self) (* Determine whether an operation ends a basic block or not. - Can be overriden for some processors to signal specific instructions + Can be overridden for some processors to signal specific instructions that terminate a basic block. *) method oper_in_basic_block = function @@ -137,7 +137,7 @@ method private instr_in_basic_block instr = | _ -> false (* Determine whether an operation is a memory store or a memory load. - Can be overriden for some processors to signal specific + Can be overridden for some processors to signal specific load or store instructions (e.g. on the I386). *) method is_store = function |