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authorXavier Leroy <xavierleroy@users.noreply.github.com>2023-05-16 11:52:31 +0200
committerGitHub <noreply@github.com>2023-05-16 11:52:31 +0200
commit8d1af245ef46e40652be4509f03ab600405aef63 (patch)
tree2e68eb707d3d6e40c1d22153aa62adf4f73e9ef7 /asmcomp/schedgen.ml
parentcd01cac2e11706cac40462f185345848596f2b40 (diff)
downloadocaml-trunk.tar.gz
Instruction scheduling: do not reorder atomic loads (#12248)HEADtrunk
Just treat atomic loads like stores. Fixes: #12216
Diffstat (limited to 'asmcomp/schedgen.ml')
-rw-r--r--asmcomp/schedgen.ml7
1 files changed, 6 insertions, 1 deletions
diff --git a/asmcomp/schedgen.ml b/asmcomp/schedgen.ml
index 2a0c75e5e1..5624281aee 100644
--- a/asmcomp/schedgen.ml
+++ b/asmcomp/schedgen.ml
@@ -181,12 +181,17 @@ method private instr_in_basic_block instr try_nesting =
Can be overridden for some processors to signal specific
load or store instructions (e.g. on the I386). *)
+(* Stores are not reordered with other stores nor with loads.
+ Loads can be reordered with other loads, but not with stores.
+ Atomic loads must not be reordered, so we treat them like stores. *)
+
method is_store = function
Istore(_, _, _) -> true
+ | Iload {is_atomic = true} -> true
| _ -> false
method is_load = function
- Iload _ -> true
+ Iload {is_atomic = false} -> true
| _ -> false
method is_checkbound = function