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authorSébastien Hinderer <seb@tarides.com>2022-12-20 10:37:46 +0100
committerGitHub <noreply@github.com>2022-12-20 10:37:46 +0100
commit59a00971056031b6da71249e771e8e45d96cfd77 (patch)
treeea1bf9a370a4c059fa792f8c0499bbfc9e84fff2
parenteb31831a960800f20ca2edd556858c00546cc178 (diff)
parent7b170f33c4e08c1bc36090f1445c18126f6621fc (diff)
downloadocaml-59a00971056031b6da71249e771e8e45d96cfd77.tar.gz
Merge pull request #11825 from eltociear/patch-4
Fix typo in emit.mlp
-rw-r--r--asmcomp/riscv/emit.mlp4
1 files changed, 2 insertions, 2 deletions
diff --git a/asmcomp/riscv/emit.mlp b/asmcomp/riscv/emit.mlp
index 859e52c463..6bb703b29d 100644
--- a/asmcomp/riscv/emit.mlp
+++ b/asmcomp/riscv/emit.mlp
@@ -364,8 +364,8 @@ let emit_instr env i =
(* ft0 is marked as destroyed for this operation *)
` fcvt.s.d ft0, {emit_reg i.arg.(0)}\n`;
` fsw ft0, {emit_int ofs}({emit_reg i.arg.(1)})\n`
- | Lop(Istore((Word_int | Word_val), Iindexed ofs, assignement)) ->
- if assignement then begin
+ | Lop(Istore((Word_int | Word_val), Iindexed ofs, assignment)) ->
+ if assignment then begin
` fence r, w\n`;
` sd {emit_reg i.arg.(0)}, {emit_int ofs}({emit_reg i.arg.(1)})\n`
end else