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* Update to use bitmask instead of bit for parked configurationHEADmasterSowjanya Komatineni2019-07-016-160/+181
| | | | | | | | | | | | | | Parked bits for SDMMC2 and SDMMC4 are part of CFGPAD register rather than pinmux registers and contains bit for each of their pins. So updating pinctrl Tegra driver to use bitmask for parked configuration rather than bit. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> [treding@nvidia.com: reshuffle fields to match driver order] [treding@nvidia.com: use bitmask 0 for unsupported] Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Do not output NVIDIA as an authorThierry Reding2019-07-011-3/+8
| | | | | | | | | Printing out the string 'NVIDIA' as the author of a file looks somewhat strange and is pretty meaningless given that there's already a copyright from NVIDIA in the files. Detect the special case and ignore it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Update kernel driver templateThierry Reding2019-07-011-16/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some changes in recent years have modified the upstream kernel driver in some ways that make it incompatible with the current template. Update the template to take into account changes introduced by the following commits: commit e3d2160f12d6aa7a87d9db09d8458b4a3492cd45 Author: Paul Gortmaker <paul.gortmaker@windriver.com> Date: Mon May 22 16:56:47 2017 -0400 pinctrl: tegra: clean up modular vs. non-modular distinctions None of the Kconfigs for any of these drivers are tristate, meaning that they currently are not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get similar changes, so they are handled in batch. We remove module.h from code that isn't doing anything modular at all; if they have __init sections, then replace it with init.h. A couple drivers have module_exit() code that is essentially orphaned, and so we remove that. Quite a few bool drivers (hence non-modular) are converted over to to builtin_platform_driver(). Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Pritesh Raithatha <praithatha@nvidia.com> Cc: Ashwini Ghuge <aghuge@nvidia.com> Cc: linux-gpio@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> commit 3c94d2d08a032d911bbe34f2edb24cb63a63644a Author: Stefan Agner <stefan@agner.ch> Date: Thu Jul 26 17:40:24 2018 +0200 pinctrl: tegra: define GPIO compatible node per SoC Tegra 2 uses a different GPIO controller which uses "tegra20-gpio" as compatible string. Make the compatible string the GPIO node is using a SoC specific property. This prevents the kernel from registering the GPIO range twice in case the GPIO range is specified in the device tree. Fixes: 9462510ce31e ("pinctrl: tegra: Only set the gpio range if needed") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> commit 1e0813ee5599932c856bda64a568895ed7a33d3a Author: Dmitry Osipenko <digetx@gmail.com> Date: Thu Aug 2 14:11:43 2018 +0300 pinctrl: tegra: Move drivers registration to arch_init level There is a bug in regards to deferred probing within the drivers core that causes GPIO-driver to suspend after its users. The bug appears if GPIO-driver probe is getting deferred, which happens after introducing dependency on PINCTRL-driver for the GPIO-driver by defining "gpio-ranges" property in device-tree. The bug in the drivers core is old (more than 4 years now) and is well known, unfortunately there is no easy fix for it. The good news is that we can workaround the deferred probe issue by changing GPIO / PINCTRL drivers registration order and hence by moving PINCTRL driver registration to the arch_init level and GPIO to the subsys_init. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Note that the last one is something that we probably should fix correctly by using device links rather than working around it by playing init level tricks. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Rename jetson-nano-sd to p3450-porgStephen Warren2019-07-012-6/+6
| | | | | | | | | This matches the downstream L4T U-Boot port, which allows the files generated by tegra-pinmux-scripts to be used directly without editing. The mandate to use name jetson-nano-sd in these scripts has been removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
* Add Jetson Nano Developer Kit (SD) BoardStephen Warren2019-06-172-0/+179
| | | | | | | v1.0 downloaded from the following URL on 2019/06/17: https://developer.nvidia.com/embedded/downloads Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Support board CSV files that obscure informationStephen Warren2019-05-091-2/+4
| | | | | | | Some board spreadsheets specify RSVD<n> for some SoC pinmux options even where the SoC does actually support some "real" option. Enhance the pinmux scripts' error checking not to throw an error when board CSVs and SoC data files don't match, in this one specific case.
* Add Colorado Engineering TK1-SOM boardPeter.Chubb@data61.csiro.au2016-08-302-0/+210
| | | | | | | | The TK1 SOM from Colorado Engineering is a small form-factor board similar to the Jetson TK1. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* soc: Get rid of .remove callbackLaxman Dewangan2016-05-031-1/+0
| | | | | | | | | | Pinctrl driver uses the devm_pinctrl_register and hence it is not required to generate code for .remove callback. Remove the need of .remove callback. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* soc: Avoid parked_reg and parked_bankLaxman Dewangan2016-05-036-10/+3
| | | | | | | | | | | | | | | | | | | | NVIDIA's Tegra210 support the park bit to make pinmux configuration enable/disable. If parked bit is 1 then configuration does not apply and if it is 0 then pinmux configuration applies. This is to support to avoid any glitch in pinmux configurations. The parked bit is part of mux register and mux bank and hence it is not required to have member for the parked_reg and parked bank very similar to other bit field of the same register. Remove the need of the parked register and parked bank and get whether parked function supported or not by parked_bit. This is to make the parked bit handling same as other fields of mux registers. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Adapt to latest U-Boot driver code changesStephen Warren2016-04-211-4/+10
| | | | | | | This makes the script generate code that matches U-Boot as of its commit "ARM: tegra: use DT bindings for GPIO naming". Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Import latest Jetson TK1 spreadsheetStephen Warren2016-04-211-1/+5
| | | | | | | | | | | | | This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* soc: Add support for Parked bits for Tegra210Rhyland Klein2016-04-076-0/+27
| | | | | | | | | Tegra210 has a parked bit for each pin. Add code to express this by updating the kernel driver MACROs to add in parked_* fields so that the kernel can handle them as it sees fit. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add the Tegra210-smaug boardRhyland Klein2016-04-072-0/+179
| | | | | | | Tegra210-smaug is the name for the Google Pixel C platform. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* remove invalid uses of rsvd1 from beaver configLucas Stach2016-02-241-15/+15
| | | | | | | Replace by actual function names of pinmux option 1. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* p2371-2180: import latest spreadsheetStephen Warren2015-09-211-19/+19
| | | | | | | | | In order to avoid any assumptions about any device connected to P2371-2180's expansion connector, the latest pinmux spreadsheet configures all muxable pins on that connector to be GPIO inputs, with on-chip pulls where appropriate. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add P2371-2180 boardStephen Warren2015-07-302-0/+179
| | | | | | P2371-2180 is a Tegra210 reference board. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* board-to-uboot: add comment re: auto-generationStephen Warren2015-07-301-0/+9
| | | | | | | | | Add a comment block to the top of each generated U-Boot header file indicating that the file was auto-generated, should not be manually edited, and with a pointer to the tool and command used to generate it. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add P2371-0000 boardStephen Warren2015-07-242-0/+179
| | | | | | P2371-0000 is a Tegra210 development board. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add E2220-1170 boardStephen Warren2015-07-242-0/+179
| | | | | | | | | | | | | | E2220-1170 is a Tegra210 reference board. The following pins have missing gpio_init_val data in the spreadsheet, and were manually fixed to be out0 per discussion with the systems engineering team: lcd_bl_en_pv1 lcd_rst_pv2 usb_vbus_en1_pcc5 Signed-off-by: Stephen Warren <swarren@nvidia.com>
* csv-to-board: allow 'Ball Name' in an abitrary columnStephen Warren2015-07-211-1/+1
| | | | | | | | | csv-to-board currently parses the header row to find out which column each desired piece of data is located in. However, it checks a hard-coded column to determine which row is the header row. Enhance the script to allow the header row identification data to be in an arbitrary column. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* csv-to-board: handle missing gpio_init_valsStephen Warren2015-07-201-0/+8
| | | | | | | | | | Some board spreadsheets have missing values in the gpio_init_val column. This occurs to handle initialization ordering quirks in downstream SW. Modify csv-to-board to handle such spreadsheets without throwing an error, but warn the user that they need to fix up the resultant config file with valid data. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for P2571 boardStephen Warren2015-06-192-0/+179
| | | | | | P2571 is an NVIDIA reference board for the Tegra210 Soc. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Support TPM on nyan boardsSimon Glass2015-05-142-4/+4
| | | | | | | There is a TPM on I2C3, so set up the pinmux for that. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* board-to-kernel-dt: don't generate outer state nodeStephen Warren2015-05-141-4/+0
| | | | | | | | | | | | | The important thing for board-to-kernel-dt to generate is the content of the pinmux "state" node in DT. The name and label of the node that contains this information is essentially irrelevant. Since this irrelevant name and label varies between boards in existing DTs, update board-to-kernel-dt so it doesn't generate it. This makes it obvious that the name and label shouldn't be modified when importing new versions of board-to-kernel-dt's output. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Support for MIPI pad ctrl groups in *.boardStephen Warren2015-03-254-7/+78
| | | | | | | Update csv-to-board.py to extract, and board-to-*.py to emit, configuration for MIPI pad ctrl groups. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for MIPI pad ctrl groups in U-Boot driver generatorStephen Warren2015-03-253-1/+74
| | | | Signed-off-by: Stephen Warren <swarren@nvidia.com>
* csv-to-board: handle missing package columnsStephen Warren2015-03-251-7/+16
| | | | | | | | Some board spreadsheets may have irrelevant package columns removed, leaving only the package column that the specific board uses. Update csv-to-board to handle missing package columns. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Fix some TAB alignment issuesStephen Warren2015-03-253-11/+21
| | | | | | | | | | | append_aligned_tabs_indent_with_tabs() was converting TABs to spaces to simplify calculation of line length, assuming the only TABs were at the beginning of the line, and hence were all exactly 8 characters wide. In some scenarios, TABs were also embedded within the line, which caused incorrect calculations. Solve this by explicitly evaluating TAB widths character by character, rather than taking shortcuts. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Remove stale FIXME in board-to-uboot.pyStephen Warren2015-03-251-1/+0
| | | | | | | | | | | The FIXME has already been fixed! Signed-off-by: Stephen Warren <swarren@nvidia.com> --- This series mainly adds support for configuring the MIPI pad control registers, along with a few fixes/cleanups first. I'll enhance the Jetson TK1 board file to actually include MIPI pad control settings as soon as I've cleared up one other change in the latest spreadsheet.
* Support Tegra210Stephen Warren2015-02-2514-227/+1572
| | | | | | | | | | | | | | | | | | | | | | | | | Tegra210 changes the pinmux HW in a few ways; at least: - The set of drive groups is much more 1:1 with the set of pins. Most pins have an associated drive group register as well as an associated pinmux register, and most drive groups cover a single pin. - Some register fields have moved from the drive group registers into the pinmux registers. - The set of available options for each pin and group varies relative to previous chips, and hence the register layouts vary a bit too. This patch updates tegra-pinmux-scripts minimally to handle these changes, to a level equivalent to the support for previous chips. For example, some new options such as per-pin schmitt aren't handled since the syseng-supplied pinmux spreadsheets don't provide a value for this option. csv-to-board-tegra124-xlsx.py is renamed to csv-to-board.py since it now supports boards using different SoCs, and it's not worth encoding all supported SoCs in the filename (Tegra30/114 aren't supported by it, hence the previous naming). Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add "submitting patches" section to READMEStephen Warren2015-02-251-0/+21
| | | | | | This tells users how/where to send patches, etc. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Only warn about unconfigured pins if they have a registerStephen Warren2015-02-171-1/+1
| | | | | | | Some pins don't have a register and hence can't be configured. Don't warn that those pins are unconfigured. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: import latest Jetson TK1 pinmuxStephen Warren2015-02-172-123/+122
| | | | | | | | | | | | | | | | | | syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content completely on correct configuration for the board/schematic, rather than the previous version which was based on the bare minimum changes relative to another reference board. The new spreadsheet sets TRISTATE for any input-only pins. This only works correctly if the global CLAMP bit is not set, so any code importing this updated version will need to be adjusted accordingly. Apparently syseng have changed their mind since the previous advice that this needed to be set:-/ This content comes from Jetson_TK1_customer_pinmux.xlsm (v09) downloaded from https://developer.nvidia.com/hardware-design-and-development. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for MIPI Pad Ctrl groups on Tegra124Stephen Warren2015-02-113-0/+127
| | | | | | | | | This aligns the output with what's check into the kernel. There are now only minor white-space/formatting differences. I'll fix those in the kernel soon, when I send patched to add Tegra210 SoC support. Cc: Sean Paul <seanpaul@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Don't set .owner field in kernel pinctrl driver any moreStephen Warren2015-02-111-1/+0
| | | | | | This aligns the output with what's checked into the kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for Nyan-bigSimon Glass2015-02-031-0/+198
| | | | | | | | | | Add support for Tegra124 Nyan-big. Pinmux is based on norrin with a single change for the reset GPIO. Signed-off-by: Simon Glass <sjg@chromium.org> [tomeu.vizoso@collabora.com: remove pull from dp_hpd_pff0] Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for Nyan-blazeTomeu Vizoso2015-01-221-0/+198
| | | | | | | Add support for Tegra124 Nyan-blaze, very similar to Nyan-big. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* add support for Beaver boardLucas Stach2015-01-091-0/+248
| | | | | | | | | This leaves some pins unconfigured, but is all I could work out from the existing U-Boot and Kernel code/DTs. Signed-off-by: Lucas Stach <dev@lynxeye.de> [added not about the data source] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* fix kernel dt generation for Tegra 3Lucas Stach2015-01-091-1/+1
| | | | | | | There is no attribute rcv_sel on Tegra 3. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Board CSV Import: Allow board configuration overrides on cmdlineStephen Warren2014-10-151-0/+8
| | | | | | | | | Add --csv FILENAME, --rsvd-0based, and --rsvd-1based command-line options to the board CSV import script. This is especially useful for Jetson TK1, since different spreadsheets use 0- and 1-based RSVD numbering, so the user may require an option to easily specify which to use. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Board CSV import: Support either 0- or 1-based RSVD numbersStephen Warren2014-10-151-1/+7
| | | | | | | | | The public Jetson TK1 pinmux spreadsheet will use 1-based RSVD numbers whereas the other internal board spreadsheets aren't (currently?) updated, and hence will continue to use 0-based RSVD numbering. Support either numbering scheme in the import script. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Board CSV import: Put full CSV filename in data structureStephen Warren2014-10-151-5/+16
| | | | | | | | | | | Putting the whole filename in to the data structure allows us to keep different CSV files in different directories. This will allow explicit separation of public and private CSV files. The per-board data is also modified to be a dictionary so that additional fields can be stored in the future. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Board CSV import: Support all Tegra124 OD pinsStephen Warren2014-10-141-2/+1
| | | | | | | Complete the list of OD pins in the CSV -> *.board import script for Tegra124. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add a README, to provide a description of the projectStephen Warren2014-09-151-0/+67
| | | | Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Make kernel driver of_device_id tables constStephen Warren2014-09-021-1/+1
| | | | | | | This updates to output to match the kernel drivers as of 5dfe10b43a91 "pinctrl: Make of_device_id array const". Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Jetson TK1: add missing PCIe-related pin configurationStephen Warren2014-08-221-0/+5
| | | | | | | | | | | | | The Jetson TK1 spreadsheet is missing configuration for the PCIe clk_req, rst, and wake pins. This causes the generated pinmux tables to also omit any configuration for these pins, which in turn causes U-Boot's and the Linux Kernel's PCIe support to fail. Manually add configuration for these pins. The values here match the values found in the downstream L4T kernel, and common sense based on the usage of these pins. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Warn about unconfigured pinsStephen Warren2014-08-213-0/+12
| | | | | | | When generating a kernel or U-Boot pinmux configuration, complain about pins that have no configuration. That's probably a bug in the spreadsheet. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for NorrinAllen Martin2014-08-042-0/+199
| | | | | | | | | Add support for Tegra124 Norrin FFD reference board (PM370). Pinmux is based on PM370_T124_customer_pinmux_1.1 spreadsheet. Signed-off-by: Allen Martin <amartin@nvidia.com> [swarren, kept supported_boards[] sorted] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Fix Venice2 sheet name in CSV import scriptStephen Warren2014-07-011-1/+1
| | | | | | | | Fix csv-to-board-tegra124-xlsx.py's comment in supported_boards{} re: the sheet that the data came from. It should be Customer_Configuration, but I was confused when I exported as CSV, and Excel renamed the sheet:-/ Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Import latest Venice2 spreadsheetStephen Warren2014-07-012-8/+4
| | | | | | | A few fixes were made to the spreadsheet, including one that removes the need for the special-case in the import script. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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