diff options
Diffstat (limited to 'src/t30')
| -rw-r--r-- | src/t30/nvbctlib_t30.c | 64 | ||||
| -rw-r--r-- | src/t30/nvboot_bct_t30.h | 88 | ||||
| -rw-r--r-- | src/t30/nvboot_sdram_param_t30.h | 382 |
3 files changed, 267 insertions, 267 deletions
diff --git a/src/t30/nvbctlib_t30.c b/src/t30/nvbctlib_t30.c index df3bef0..2cb7ab8 100644 --- a/src/t30/nvbctlib_t30.c +++ b/src/t30/nvbctlib_t30.c @@ -59,22 +59,22 @@ case token_bl_##x:\ #define CASE_GET_NVU32(id) \ case token_##id:\ if (bct == NULL) return -ENODATA; \ - *((u_int32_t *)data) = bct_ptr->id; \ + *((uint32_t *)data) = bct_ptr->id; \ break #define CASE_GET_CONST(id, val) \ case token_##id:\ - *((u_int32_t *)data) = val; \ + *((uint32_t *)data) = val; \ break #define CASE_GET_CONST_PREFIX(id, val_prefix) \ case token_##id:\ - *((u_int32_t *)data) = val_prefix##_##id; \ + *((uint32_t *)data) = val_prefix##_##id; \ break #define CASE_SET_NVU32(id) \ case token_##id:\ - bct_ptr->id = *((u_int32_t *)data); \ + bct_ptr->id = *((uint32_t *)data); \ break #define CASE_GET_DATA(id, size) \ @@ -113,9 +113,9 @@ parse_token t30_root_token_list[] = { int t30_set_dev_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t value) + uint32_t value) { nvboot_config_table *bct = NULL; @@ -164,9 +164,9 @@ t30_set_dev_param(build_image_context *context, int t30_get_dev_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t *value) + uint32_t *value) { nvboot_config_table *bct = NULL; @@ -213,9 +213,9 @@ t30_get_dev_param(build_image_context *context, int t30_get_sdram_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t *value) + uint32_t *value) { nvboot_sdram_params *params; nvboot_config_table *bct = NULL; @@ -427,9 +427,9 @@ t30_get_sdram_param(build_image_context *context, int t30_set_sdram_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t value) + uint32_t value) { nvboot_sdram_params *params; nvboot_config_table *bct = NULL; @@ -642,10 +642,10 @@ t30_set_sdram_param(build_image_context *context, } int -t30_getbl_param(u_int32_t set, +t30_getbl_param(uint32_t set, parse_token id, - u_int32_t *data, - u_int8_t *bct) + uint32_t *data, + uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -677,10 +677,10 @@ t30_getbl_param(u_int32_t set, } int -t30_setbl_param(u_int32_t set, +t30_setbl_param(uint32_t set, parse_token id, - u_int32_t *data, - u_int8_t *bct) + uint32_t *data, + uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -712,7 +712,7 @@ t30_setbl_param(u_int32_t set, } int -t30_bct_get_value(parse_token id, void *data, u_int8_t *bct) +t30_bct_get_value(parse_token id, void *data, uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; nvboot_config_table samplebct; /* Used for computing offsets. */ @@ -740,13 +740,13 @@ t30_bct_get_value(parse_token id, void *data, u_int8_t *bct) case token_block_size: if (bct == NULL) return -ENODATA; - *((u_int32_t *)data) = 1 << bct_ptr->block_size_log2; + *((uint32_t *)data) = 1 << bct_ptr->block_size_log2; break; case token_page_size: if (bct == NULL) return -ENODATA; - *((u_int32_t *)data) = 1 << bct_ptr->page_size_log2; + *((uint32_t *)data) = 1 << bct_ptr->page_size_log2; break; /* @@ -757,25 +757,25 @@ t30_bct_get_value(parse_token id, void *data, u_int8_t *bct) CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE); case token_reserved_offset: - *((u_int32_t *)data) = (u_int8_t *)&(samplebct.reserved) - - (u_int8_t *)&samplebct; + *((uint32_t *)data) = (uint8_t *)&(samplebct.reserved) + - (uint8_t *)&samplebct; break; case token_bct_size: - *((u_int32_t *)data) = sizeof(nvboot_config_table); + *((uint32_t *)data) = sizeof(nvboot_config_table); break; CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); case token_crypto_offset: /* Offset to region in BCT to encrypt & sign */ - *((u_int32_t *)data) = (u_int8_t *)&(samplebct.random_aes_blk) - - (u_int8_t *)&samplebct; + *((uint32_t *)data) = (uint8_t *)&(samplebct.random_aes_blk) + - (uint8_t *)&samplebct; break; case token_crypto_length: /* size of region in BCT to encrypt & sign */ - *((u_int32_t *)data) = sizeof(nvboot_config_table) - sizeof(nvboot_hash); + *((uint32_t *)data) = sizeof(nvboot_config_table) - sizeof(nvboot_hash); break; CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); @@ -803,7 +803,7 @@ t30_bct_get_value(parse_token id, void *data, u_int8_t *bct) } int -t30_bct_set_value(parse_token id, void *data, u_int8_t *bct) +t30_bct_set_value(parse_token id, void *data, uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -832,9 +832,9 @@ t30_bct_set_value(parse_token id, void *data, u_int8_t *bct) int t30_bct_set_data(parse_token id, - u_int8_t *data, - u_int32_t length, - u_int8_t *bct) + uint8_t *data, + uint32_t length, + uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -870,7 +870,7 @@ int t30_bct_token_supported(parse_token token) void t30_init_bad_block_table(build_image_context *context) { - u_int32_t bytes_per_entry; + uint32_t bytes_per_entry; nvboot_badblock_table *table; nvboot_config_table *bct; diff --git a/src/t30/nvboot_bct_t30.h b/src/t30/nvboot_bct_t30.h index 39c998e..84c6d3b 100644 --- a/src/t30/nvboot_bct_t30.h +++ b/src/t30/nvboot_bct_t30.h @@ -97,7 +97,7 @@ enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; * Defines the storage for a hash value (128 bits). */ typedef struct nvboot_hash_rec { - u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; } nvboot_hash; /** @@ -109,63 +109,63 @@ typedef struct nvboot_nand_params_rec { * If it is set to 18, then clock source to Nand controller is * 432 / 18 = 24MHz. */ - u_int8_t clock_divider; + uint8_t clock_divider; /** * Specifies the value to be programmed to Nand Async Timing * Register 0 */ - u_int32_t async_timing0; + uint32_t async_timing0; /** * Specifies the value to be programmed to Nand Async Timing * Register 1 */ - u_int32_t async_timing1; + uint32_t async_timing1; /** * Specifies the value to be programmed to Nand Async Timing * Register 2 */ - u_int32_t async_timing2; + uint32_t async_timing2; /** * Specifies the value to be programmed to Nand Async Timing * Register 3 */ - u_int32_t async_timing3; + uint32_t async_timing3; /** * Specifies the value to be programmed to Nand Sync DDR Timing * Register 0 */ - u_int32_t sddr_timing0; + uint32_t sddr_timing0; /** * Specifies the value to be programmed to Nand Sync DDR Timing * Register 1 */ - u_int32_t sddr_timing1; + uint32_t sddr_timing1; /** * Specifies the value to be programmed to Nand Toggle DDR Timing * Register 0 */ - u_int32_t tddr_timing0; + uint32_t tddr_timing0; /** * Specifies the value to be programmed to Nand Toggle DDR Timing * Register 1 */ - u_int32_t tddr_timing1; + uint32_t tddr_timing1; /* Specifies the value to be programmed to FBIO_DQSIB_DELAY register */ - u_int8_t fbio_dqsib_dly_byte; + uint8_t fbio_dqsib_dly_byte; /* Specifies the value to be programmed to FBIO_DQUSE_DELAY register */ - u_int8_t fbio_quse_dly_byte; + uint8_t fbio_quse_dly_byte; /* Specifies the CFG_QUSE_LATE value to be programmed to FBIO * configuration register */ - u_int8_t fbio_cfg_quse_late; + uint8_t fbio_cfg_quse_late; /* Specifies whether to enable sync DDR more or not */ - u_int8_t disable_sync_ddr; + uint8_t disable_sync_ddr; /* Specifies the block size in log2 bytes */ - u_int8_t block_size_log2; + uint8_t block_size_log2; /* Specifies the page size in log2 bytes */ - u_int8_t page_size_log2; + uint8_t page_size_log2; } nvboot_nand_params; /* Defines various data widths supported. */ @@ -212,7 +212,7 @@ typedef struct nvboot_sdmmc_params_rec { * which is PLLP running at 432MHz. If it is set to 18, then the SDMMC * controller runs at 432/18 = 24MHz. */ - u_int8_t clock_divider; + uint8_t clock_divider; /* Specifies the data bus width. Supported data widths are 4/8 bits. */ nvboot_sdmmc_data_width data_width; @@ -223,7 +223,7 @@ typedef struct nvboot_sdmmc_params_rec { * supported within the power class range (0 to Max) if the selected * data width cannot be used at the chosen clock frequency. */ - u_int8_t max_power_class_supported; + uint8_t max_power_class_supported; /* Specifies the SD controller to be selected */ nvboot_sdmmc_cntrl sd_controller; @@ -266,21 +266,21 @@ typedef struct nvboot_spiflash_params_rec { * FAST_READ at 40MHz: 11 * FAST_READ at 50MHz: 9 */ - u_int8_t clock_divider; + uint8_t clock_divider; /** * Specifies the type of command for read operations. * NV_FALSE specifies a NORMAL_READ Command * NV_TRUE specifies a FAST_READ Command */ - u_int8_t read_command_type_fast; + uint8_t read_command_type_fast; } nvboot_spiflash_params; /** * Defines the union of the parameters required by each device. */ typedef union { - u_int8_t size[64]; + uint8_t size[64]; /* Specifies optimized parameters for NAND */ nvboot_nand_params nand_params; /* Specifies optimized parameters for eMMC and eSD */ @@ -321,13 +321,13 @@ typedef enum { * the device. */ typedef struct nv_bootloader_info_rec { - u_int32_t version; - u_int32_t start_blk; - u_int32_t start_page; - u_int32_t length; - u_int32_t load_addr; - u_int32_t entry_point; - u_int32_t attribute; + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; nvboot_hash crypto_hash; } nv_bootloader_info; @@ -335,10 +335,10 @@ typedef struct nv_bootloader_info_rec { * Defines the bad block table structure stored in the BCT. */ typedef struct nvboot_badblock_table_rec { - u_int32_t entries_used; - u_int8_t virtual_blk_size_log2; - u_int8_t block_size_log2; - u_int8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; } nvboot_badblock_table; /** @@ -352,28 +352,28 @@ typedef struct nvboot_badblock_table_rec { typedef struct nvboot_config_table_rec { nvboot_hash crypto_hash; nvboot_hash random_aes_blk; - u_int32_t boot_data_version; - u_int32_t block_size_log2; - u_int32_t page_size_log2; - u_int32_t partition_size; - u_int32_t num_param_sets; + uint32_t boot_data_version; + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; - u_int32_t num_sdram_sets; + uint32_t num_sdram_sets; nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; nvboot_badblock_table badblock_table; - u_int32_t bootloader_used; + uint32_t bootloader_used; nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; - u_int8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; /* * ODMDATA is stored in the BCT in IRAM by the BootROM. * Read the data @ bct_start + (bct_size - 12). This works * on T20 and T30 BCTs, which are locked down. If this changes * in new chips, we can revisit this algorithm. */ - u_int32_t odm_data; - u_int32_t reserved1; - u_int8_t enable_fail_back; - u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; + uint32_t odm_data; + uint32_t reserved1; + uint8_t enable_fail_back; + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; } nvboot_config_table; #endif /* #ifndef INCLUDED_NVBOOT_BCT_T30_H */ diff --git a/src/t30/nvboot_sdram_param_t30.h b/src/t30/nvboot_sdram_param_t30.h index 18d77d7..ab6d536 100644 --- a/src/t30/nvboot_sdram_param_t30.h +++ b/src/t30/nvboot_sdram_param_t30.h @@ -63,299 +63,299 @@ typedef struct nvboot_sdram_params_rec { /* MC/EMC clock source configuration */ /* Specifies the CPCON value for PllM */ - u_int32_t pllm_charge_pump_setup_ctrl; + uint32_t pllm_charge_pump_setup_ctrl; /* Specifies the LPCON value for PllM */ - u_int32_t pllm_loop_filter_setup_ctrl; + uint32_t pllm_loop_filter_setup_ctrl; /* Specifies the M value for PllM */ - u_int32_t pllm_input_divider; + uint32_t pllm_input_divider; /* Specifies the N value for PllM */ - u_int32_t pllm_feedback_divider; + uint32_t pllm_feedback_divider; /* Specifies the P value for PllM */ - u_int32_t pllm_post_divider; + uint32_t pllm_post_divider; /* Specifies the time to wait for PLLM to lock (in microseconds) */ - u_int32_t pllm_stable_time; + uint32_t pllm_stable_time; /* Specifies the divider for the EMC Clock Source */ - u_int32_t emc_clock_divider; + uint32_t emc_clock_divider; /* Specifies the PLL source for the EMC Clock Source */ - u_int32_t emc_clock_source; + uint32_t emc_clock_source; /* * Specifies the enable for using low jitter clock for * the EMC Clock Source */ - u_int32_t emc_clock_use_pll_mud; + uint32_t emc_clock_use_pll_mud; /* Auto-calibration of EMC pads */ /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - u_int32_t emc_auto_cal_interval; + uint32_t emc_auto_cal_interval; /* * Specifies the value for EMC_AUTO_CAL_CONFIG * Note: Trigger bits are set by the SDRAM code. */ - u_int32_t emc_auto_cal_config; + uint32_t emc_auto_cal_config; /* * Specifies the time for the calibration * to stabilize (in microseconds) */ - u_int32_t emc_auto_cal_wait; + uint32_t emc_auto_cal_wait; /* * DRAM size information * Specifies the value for EMC_ADR_CFG */ - u_int32_t emc_adr_cfg; + uint32_t emc_adr_cfg; /* * Specifies the time to wait after asserting pin * CKE (in microseconds) */ - u_int32_t emc_pin_program_wait; + uint32_t emc_pin_program_wait; /* Specifies the extra delay before/after pin RESET/CKE command */ - u_int32_t emc_pin_extra_wait; + uint32_t emc_pin_extra_wait; /* * Specifies the extra delay after the first writing * of EMC_TIMING_CONTROL */ - u_int32_t emc_timing_control_wait; + uint32_t emc_timing_control_wait; /* Timing parameters required for the SDRAM */ /* Specifies the value for EMC_RC */ - u_int32_t emc_rc; + uint32_t emc_rc; /* Specifies the value for EMC_RFC */ - u_int32_t emc_rfc; + uint32_t emc_rfc; /* Specifies the value for EMC_RAS */ - u_int32_t emc_ras; + uint32_t emc_ras; /* Specifies the value for EMC_RP */ - u_int32_t emc_rp; + uint32_t emc_rp; /* Specifies the value for EMC_R2W */ - u_int32_t emc_r2w; + uint32_t emc_r2w; /* Specifies the value for EMC_R2W */ - u_int32_t emc_w2r; + uint32_t emc_w2r; /* Specifies the value for EMC_R2P */ - u_int32_t emc_r2p; + uint32_t emc_r2p; /* Specifies the value for EMC_W2P */ - u_int32_t emc_w2p; + uint32_t emc_w2p; /* Specifies the value for EMC_RD_RCD */ - u_int32_t emc_rd_rcd; + uint32_t emc_rd_rcd; /* Specifies the value for EMC_WR_RCD */ - u_int32_t emc_wr_rcd; + uint32_t emc_wr_rcd; /* Specifies the value for EMC_RRD */ - u_int32_t emc_rrd; + uint32_t emc_rrd; /* Specifies the value for EMC_REXT */ - u_int32_t emc_rext; + uint32_t emc_rext; /* Specifies the value for EMC_WEXT */ - u_int32_t emc_wext; + uint32_t emc_wext; /* Specifies the value for EMC_WDV */ - u_int32_t emc_wdv; + uint32_t emc_wdv; /* Specifies the value for EMC_QUSE */ - u_int32_t emc_quse; + uint32_t emc_quse; /* Specifies the value for EMC_QRST */ - u_int32_t emc_qrst; + uint32_t emc_qrst; /* Specifies the value for EMC_QSAFE */ - u_int32_t emc_qsafe; + uint32_t emc_qsafe; /* Specifies the value for EMC_RDV */ - u_int32_t emc_rdv; + uint32_t emc_rdv; /* Specifies the value for EMC_CTT */ - u_int32_t emc_ctt; + uint32_t emc_ctt; /* Specifies the value for EMC_CTT_DURATION */ - u_int32_t emc_ctt_duration; + uint32_t emc_ctt_duration; /* Specifies the value for EMC_REFRESH */ - u_int32_t emc_refresh; + uint32_t emc_refresh; /* Specifies the value for EMC_BURST_REFRESH_NUM */ - u_int32_t emc_burst_refresh_num; + uint32_t emc_burst_refresh_num; /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - u_int32_t emc_prerefresh_req_cnt; + uint32_t emc_prerefresh_req_cnt; /* Specifies the value for EMC_PDEX2WR */ - u_int32_t emc_pdex2wr; + uint32_t emc_pdex2wr; /* Specifies the value for EMC_PDEX2RD */ - u_int32_t emc_pdex2rd; + uint32_t emc_pdex2rd; /* Specifies the value for EMC_PCHG2PDEN */ - u_int32_t emc_pchg2pden; + uint32_t emc_pchg2pden; /* Specifies the value for EMC_ACT2PDEN */ - u_int32_t emc_act2pden; + uint32_t emc_act2pden; /* Specifies the value for EMC_AR2PDEN */ - u_int32_t emc_ar2pden; + uint32_t emc_ar2pden; /* Specifies the value for EMC_RW2PDEN */ - u_int32_t emc_rw2pden; + uint32_t emc_rw2pden; /* Specifies the value for EMC_TXSR */ - u_int32_t emc_txsr; + uint32_t emc_txsr; /* Specifies the value for EMC_TXSRDLL */ - u_int32_t emc_txsr_dll; + uint32_t emc_txsr_dll; /* Specifies the value for EMC_TCKE */ - u_int32_t emc_tcke; + uint32_t emc_tcke; /* Specifies the value for EMC_TFAW */ - u_int32_t emc_tfaw; + uint32_t emc_tfaw; /* Specifies the value for EMC_TRPAB */ - u_int32_t emc_trpab; + uint32_t emc_trpab; /* Specifies the value for EMC_TCLKSTABLE */ - u_int32_t emc_tclkstable; + uint32_t emc_tclkstable; /* Specifies the value for EMC_TCLKSTOP */ - u_int32_t emc_tclkstop; + uint32_t emc_tclkstop; /* Specifies the value for EMC_TREFBW */ - u_int32_t emc_trefbw; + uint32_t emc_trefbw; /* Specifies the value for EMC_QUSE_EXTRA */ - u_int32_t emc_quse_extra; + uint32_t emc_quse_extra; /* FBIO configuration values */ /* Specifies the value for EMC_FBIO_CFG5 */ - u_int32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg5; /* Specifies the value for EMC_FBIO_CFG6 */ - u_int32_t emc_fbio_cfg6; + uint32_t emc_fbio_cfg6; /* Specifies the value for EMC_FBIO_SPARE */ - u_int32_t emc_fbio_spare; + uint32_t emc_fbio_spare; /* Specifies the value for EMC_CFG_RSV */ - u_int32_t emc_cfg_rsv; + uint32_t emc_cfg_rsv; /* MRS command values */ /* Specifies the value for EMC_MRS */ - u_int32_t emc_mrs; + uint32_t emc_mrs; /* Specifies the value for EMC_EMRS */ - u_int32_t emc_emrs; + uint32_t emc_emrs; /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - u_int32_t emc_mrw1; + uint32_t emc_mrw1; /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - u_int32_t emc_mrw2; + uint32_t emc_mrw2; /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - u_int32_t emc_mrw3; + uint32_t emc_mrw3; /* * Specifies the programming to extra LPDDR2 Mode Register * at cold boot */ - u_int32_t emc_mrw_extra; + uint32_t emc_mrw_extra; /* Specifies the programming to LPDDR2 Mode Register 1 at warm boot */ - u_int32_t emc_warm_boot_mrw1; + uint32_t emc_warm_boot_mrw1; /* Specifies the programming to LPDDR2 Mode Register 2 at warm boot */ - u_int32_t emc_warm_boot_mrw2; + uint32_t emc_warm_boot_mrw2; /* Specifies the programming to LPDDR2 Mode Register 3 at warm boot */ - u_int32_t emc_warm_boot_mrw3; + uint32_t emc_warm_boot_mrw3; /* * Specifies the programming to extra LPDDR2 Mode Register * at warm boot */ - u_int32_t emc_warm_boot_mrw_extra; + uint32_t emc_warm_boot_mrw_extra; /* * Specify the enable of extra Mode Register programming at * warm boot */ - u_int32_t emc_warm_boot_extramode_reg_write_enable; + uint32_t emc_warm_boot_extramode_reg_write_enable; /* * Specify the enable of extra Mode Register programming at * cold boot */ - u_int32_t emc_extramode_reg_write_enable; + uint32_t emc_extramode_reg_write_enable; /* Specifies the EMC_MRW reset command value */ - u_int32_t emc_mrw_reset_command; + uint32_t emc_mrw_reset_command; /* Specifies the EMC Reset wait time (in microseconds) */ - u_int32_t emc_mrw_reset_ninit_wait; + uint32_t emc_mrw_reset_ninit_wait; /* Specifies the value for EMC_MRS_WAIT_CNT */ - u_int32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt; /* EMC miscellaneous configurations */ /* Specifies the value for EMC_CFG */ - u_int32_t emc_cfg; + uint32_t emc_cfg; /* Specifies the value for EMC_CFG_2 */ - u_int32_t emc_cfg2; + uint32_t emc_cfg2; /* Specifies the value for EMC_DBG */ - u_int32_t emc_dbg; + uint32_t emc_dbg; /* Specifies the value for EMC_CMDQ */ - u_int32_t emc_cmd_q; + uint32_t emc_cmd_q; /* Specifies the value for EMC_MC2EMCQ */ - u_int32_t emc_mc2emc_q; + uint32_t emc_mc2emc_q; /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - u_int32_t emc_dyn_self_ref_control; + uint32_t emc_dyn_self_ref_control; /* Specifies the value for MEM_INIT_DONE */ - u_int32_t ahb_arbitration_xbar_ctrl_meminit_done; + uint32_t ahb_arbitration_xbar_ctrl_meminit_done; /* Specifies the value for EMC_CFG_DIG_DLL */ - u_int32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll; /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - u_int32_t emc_cfg_dig_dll_period; + uint32_t emc_cfg_dig_dll_period; /* Specifies the vlaue of *DEV_SELECTN of various EMC registers */ - u_int32_t emc_dev_select; + uint32_t emc_dev_select; /* Specifies the value for EMC_SEL_DPD_CTRL */ - u_int32_t emc_sel_dpd_ctrl; + uint32_t emc_sel_dpd_ctrl; /* Pads trimmer delays */ /* Specifies the value for EMC_DLL_XFORM_DQS0 */ - u_int32_t emc_dll_xform_dqs0; + uint32_t emc_dll_xform_dqs0; /* Specifies the value for EMC_DLL_XFORM_DQS1 */ - u_int32_t emc_dll_xform_dqs1; + uint32_t emc_dll_xform_dqs1; /* Specifies the value for EMC_DLL_XFORM_DQS2 */ - u_int32_t emc_dll_xform_dqs2; + uint32_t emc_dll_xform_dqs2; /* Specifies the value for EMC_DLL_XFORM_DQS3 */ - u_int32_t emc_dll_xform_dqs3; + uint32_t emc_dll_xform_dqs3; /* Specifies the value for EMC_DLL_XFORM_DQS4 */ - u_int32_t emc_dll_xform_dqs4; + uint32_t emc_dll_xform_dqs4; /* Specifies the value for EMC_DLL_XFORM_DQS5 */ - u_int32_t emc_dll_xform_dqs5; + uint32_t emc_dll_xform_dqs5; /* Specifies the value for EMC_DLL_XFORM_DQS6 */ - u_int32_t emc_dll_xform_dqs6; + uint32_t emc_dll_xform_dqs6; /* Specifies the value for EMC_DLL_XFORM_DQS7 */ - u_int32_t emc_dll_xform_dqs7; + uint32_t emc_dll_xform_dqs7; /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ - u_int32_t emc_dll_xform_quse0; + uint32_t emc_dll_xform_quse0; /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ - u_int32_t emc_dll_xform_quse1; + uint32_t emc_dll_xform_quse1; /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ - u_int32_t emc_dll_xform_quse2; + uint32_t emc_dll_xform_quse2; /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ - u_int32_t emc_dll_xform_quse3; + uint32_t emc_dll_xform_quse3; /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ - u_int32_t emc_dll_xform_quse4; + uint32_t emc_dll_xform_quse4; /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ - u_int32_t emc_dll_xform_quse5; + uint32_t emc_dll_xform_quse5; /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ - u_int32_t emc_dll_xform_quse6; + uint32_t emc_dll_xform_quse6; /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ - u_int32_t emc_dll_xform_quse7; + uint32_t emc_dll_xform_quse7; /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ - u_int32_t emc_dli_trim_tx_dqs0; + uint32_t emc_dli_trim_tx_dqs0; /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ - u_int32_t emc_dli_trim_tx_dqs1; + uint32_t emc_dli_trim_tx_dqs1; /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ - u_int32_t emc_dli_trim_tx_dqs2; + uint32_t emc_dli_trim_tx_dqs2; /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ - u_int32_t emc_dli_trim_tx_dqs3; + uint32_t emc_dli_trim_tx_dqs3; /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ - u_int32_t emc_dli_trim_tx_dqs4; + uint32_t emc_dli_trim_tx_dqs4; /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ - u_int32_t emc_dli_trim_tx_dqs5; + uint32_t emc_dli_trim_tx_dqs5; /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ - u_int32_t emc_dli_trim_tx_dqs6; + uint32_t emc_dli_trim_tx_dqs6; /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ - u_int32_t emc_dli_trim_tx_dqs7; + uint32_t emc_dli_trim_tx_dqs7; /* Specifies the value for EMC_DLL_XFORM_DQ0 */ - u_int32_t emc_dll_xform_dq0; + uint32_t emc_dll_xform_dq0; /* Specifies the value for EMC_DLL_XFORM_DQ1 */ - u_int32_t emc_dll_xform_dq1; + uint32_t emc_dll_xform_dq1; /* Specifies the value for EMC_DLL_XFORM_DQ2 */ - u_int32_t emc_dll_xform_dq2; + uint32_t emc_dll_xform_dq2; /* Specifies the value for EMC_DLL_XFORM_DQ3 */ - u_int32_t emc_dll_xform_dq3; + uint32_t emc_dll_xform_dq3; /* * Specifies the delay after asserting CKE pin during a WarmBoot0 * sequence (in microseconds) */ - u_int32_t warm_boot_wait; + uint32_t warm_boot_wait; /* Specifies the value for EMC_CTT_TERM_CTRL */ - u_int32_t emc_ctt_term_ctrl; + uint32_t emc_ctt_term_ctrl; /* Specifies the value for EMC_ODT_WRITE */ - u_int32_t emc_odt_write; + uint32_t emc_odt_write; /* Specifies the value for EMC_ODT_WRITE */ - u_int32_t emc_odt_read; + uint32_t emc_odt_read; /* Periodic ZQ calibration */ @@ -363,204 +363,204 @@ typedef struct nvboot_sdram_params_rec { * Specifies the value for EMC_ZCAL_INTERVAL * Value 0 disables ZQ calibration */ - u_int32_t emc_zcal_interval; + uint32_t emc_zcal_interval; /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - u_int32_t emc_zcal_wait_cnt; + uint32_t emc_zcal_wait_cnt; /* Specifies the value for EMC_ZCAL_MRW_CMD */ - u_int32_t emc_zcal_mrw_cmd; + uint32_t emc_zcal_mrw_cmd; /* DRAM initialization sequence flow control */ /* Specifies the MRS command value for resetting DLL */ - u_int32_t emc_mrs_reset_dll; + uint32_t emc_mrs_reset_dll; /* Specifies the command for ZQ initialization of device 0 */ - u_int32_t emc_zcal_init_dev0; + uint32_t emc_zcal_init_dev0; /* Specifies the command for ZQ initialization of device 1 */ - u_int32_t emc_zcal_init_dev1; + uint32_t emc_zcal_init_dev1; /* * Specifies the wait time after programming a ZQ initialization * command (in microseconds) */ - u_int32_t emc_zcal_init_wait; + uint32_t emc_zcal_init_wait; /* Specifies the enable for ZQ calibration at cold boot */ - u_int32_t emc_zcal_cold_boot_enable; + uint32_t emc_zcal_cold_boot_enable; /* Specifies the enable for ZQ calibration at warm boot */ - u_int32_t emc_zcal_warm_boot_enable; + uint32_t emc_zcal_warm_boot_enable; /* * Specifies the MRW command to LPDDR2 for ZQ calibration *on warmboot */ /* Is issued to both devices separately */ - u_int32_t emc_mrw_lpddr2zcal_warm_boot; + uint32_t emc_mrw_lpddr2zcal_warm_boot; /* * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot * Is issued to both devices separately */ - u_int32_t emc_zqcal_ddr3_warm_boot; + uint32_t emc_zqcal_ddr3_warm_boot; /* * Specifies the wait time for ZQ calibration on warmboot * (in microseconds) */ - u_int32_t emc_zcal_warm_boot_wait; + uint32_t emc_zcal_warm_boot_wait; /* * Specifies the enable for DRAM Mode Register programming * at warm boot */ - u_int32_t emc_mrs_warm_boot_enable; + uint32_t emc_mrs_warm_boot_enable; /* * Specifies the wait time after sending an MRS DLL reset command * in microseconds) */ - u_int32_t emc_mrs_reset_dll_wait; + uint32_t emc_mrs_reset_dll_wait; /* * Specifies the first of two EMRS commands to initialize mode * registers */ - u_int32_t emc_emrs_emr2; + uint32_t emc_emrs_emr2; /* * Specifies the second of two EMRS commands to initialize mode * registers */ - u_int32_t emc_emrs_emr3; + uint32_t emc_emrs_emr3; /* Specifies the extra MRS command to initialize mode registers */ - u_int32_t emc_mrs_extra; + uint32_t emc_mrs_extra; /* Specifies the programming to DDR3 Mode Register 0 at warm boot */ - u_int32_t emc_warm_boot_mrs; + uint32_t emc_warm_boot_mrs; /* Specifies the programming to DDR3 Mode Register 1 at warm boot */ - u_int32_t emc_warm_boot_emrs; + uint32_t emc_warm_boot_emrs; /* Specifies the programming to DDR3 Mode Register 2 at warm boot */ - u_int32_t emc_warm_boot_emr2; + uint32_t emc_warm_boot_emr2; /* Specifies the programming to DDR3 Mode Register 3 at warm boot */ - u_int32_t emc_warm_boot_emr3; + uint32_t emc_warm_boot_emr3; /* Specifies the extra MRS command at warm boot */ - u_int32_t emc_warm_boot_mrs_extra; + uint32_t emc_warm_boot_mrs_extra; /* Specifies the EMRS command to enable the DDR2 DLL */ - u_int32_t emc_emrs_ddr2_dll_enable; + uint32_t emc_emrs_ddr2_dll_enable; /* Specifies the MRS command to reset the DDR2 DLL */ - u_int32_t emc_mrs_ddr2_dll_reset; + uint32_t emc_mrs_ddr2_dll_reset; /* Specifies the EMRS command to set OCD calibration */ - u_int32_t emc_emrs_ddr2_ocd_calib; + uint32_t emc_emrs_ddr2_ocd_calib; /* * Specifies the wait between initializing DDR and setting OCD * calibration (in microseconds) */ - u_int32_t emc_ddr2_wait; + uint32_t emc_ddr2_wait; /* Specifies the value for EMC_CLKEN_OVERRIDE */ - u_int32_t emc_clken_override; + uint32_t emc_clken_override; /* * Specifies LOG2 of the extra refresh numbers after booting * Program 0 to disable */ - u_int32_t emc_extra_refresh_num; + uint32_t emc_extra_refresh_num; /* Specifies the master override for all EMC clocks */ - u_int32_t emc_clken_override_allwarm_boot; + uint32_t emc_clken_override_allwarm_boot; /* Specifies the master override for all MC clocks */ - u_int32_t mc_clken_override_allwarm_boot; + uint32_t mc_clken_override_allwarm_boot; /* Specifies digital dll period, choosing between 4 to 64 ms */ - u_int32_t emc_cfg_dig_dll_period_warm_boot; + uint32_t emc_cfg_dig_dll_period_warm_boot; /* Pad controls */ /* Specifies the value for PMC_VDDP_SEL */ - u_int32_t pmc_vddp_sel; + uint32_t pmc_vddp_sel; /* Specifies the value for PMC_DDR_PWR */ - u_int32_t pmc_ddr_pwr; + uint32_t pmc_ddr_pwr; /* Specifies the value for PMC_DDR_CFG */ - u_int32_t pmc_ddr_cfg; + uint32_t pmc_ddr_cfg; /* Specifies the value for PMC_IO_DPD_REQ */ - u_int32_t pmc_io_dpd_req; + uint32_t pmc_io_dpd_req; /* Specifies the value for PMC_E_NO_VTTGEN */ - u_int32_t pmc_eno_vtt_gen; + uint32_t pmc_eno_vtt_gen; /* Specifies the value for PMC_NO_IOPOWER */ - u_int32_t pmc_no_io_power; + uint32_t pmc_no_io_power; /* Specifies the value for EMC_XM2CMDPADCTRL */ - u_int32_t emc_xm2cmd_pad_ctrl; + uint32_t emc_xm2cmd_pad_ctrl; /* Specifies the value for EMC_XM2CMDPADCTRL2 */ - u_int32_t emc_xm2cmd_pad_ctrl2; + uint32_t emc_xm2cmd_pad_ctrl2; /* Specifies the value for EMC_XM2DQSPADCTRL */ - u_int32_t emc_xm2dqs_pad_ctrl; + uint32_t emc_xm2dqs_pad_ctrl; /* Specifies the value for EMC_XM2DQSPADCTRL2 */ - u_int32_t emc_xm2dqs_pad_ctrl2; + uint32_t emc_xm2dqs_pad_ctrl2; /* Specifies the value for EMC_XM2DQSPADCTRL3 */ - u_int32_t emc_xm2dqs_pad_ctrl3; + uint32_t emc_xm2dqs_pad_ctrl3; /* Specifies the value for EMC_XM2DQPADCTRL */ - u_int32_t emc_xm2dq_pad_ctrl; + uint32_t emc_xm2dq_pad_ctrl; /* Specifies the value for EMC_XM2DQPADCTRL2 */ - u_int32_t emc_xm2dq_pad_ctrl2; + uint32_t emc_xm2dq_pad_ctrl2; /* Specifies the value for EMC_XM2CLKPADCTRL */ - u_int32_t emc_xm2clk_pad_ctrl; + uint32_t emc_xm2clk_pad_ctrl; /* Specifies the value for EMC_XM2COMPPADCTRL */ - u_int32_t emc_xm2comp_pad_ctrl; + uint32_t emc_xm2comp_pad_ctrl; /* Specifies the value for EMC_XM2VTTGENPADCTRL */ - u_int32_t emc_xm2vttgen_pad_ctrl; + uint32_t emc_xm2vttgen_pad_ctrl; /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ - u_int32_t emc_xm2vttgen_pad_ctrl2; + uint32_t emc_xm2vttgen_pad_ctrl2; /* Specifies the value for EMC_XM2QUSEPADCTRL */ - u_int32_t emc_xm2quse_pad_ctrl; + uint32_t emc_xm2quse_pad_ctrl; /* DRAM size information */ /* Specifies the value for MC_EMEM_ADR_CFG */ - u_int32_t mc_emem_adr_cfg; + uint32_t mc_emem_adr_cfg; /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - u_int32_t mc_emem_adr_cfg_dev0; + uint32_t mc_emem_adr_cfg_dev0; /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - u_int32_t mc_emem_adr_cfg_dev1; + uint32_t mc_emem_adr_cfg_dev1; /* * Specifies the value for MC_EMEM_CFG which holds the external memory * size (in KBytes) */ - u_int32_t mc_emem_cfg; + uint32_t mc_emem_cfg; /* MC arbitration configuration */ /* Specifies the value for MC_EMEM_ARB_CFG */ - u_int32_t mc_emem_arb_cfg; + uint32_t mc_emem_arb_cfg; /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - u_int32_t mc_emem_arb_outstanding_req; + uint32_t mc_emem_arb_outstanding_req; /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - u_int32_t mc_emem_arb_timing_rcd; + uint32_t mc_emem_arb_timing_rcd; /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - u_int32_t mc_emem_arb_timing_rp; + uint32_t mc_emem_arb_timing_rp; /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - u_int32_t mc_emem_arb_timing_rc; + uint32_t mc_emem_arb_timing_rc; /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - u_int32_t mc_emem_arb_timing_ras; + uint32_t mc_emem_arb_timing_ras; /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - u_int32_t mc_emem_arb_timing_faw; + uint32_t mc_emem_arb_timing_faw; /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - u_int32_t mc_emem_arb_timing_rrd; + uint32_t mc_emem_arb_timing_rrd; /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - u_int32_t mc_emem_arb_timing_rap2pre; + uint32_t mc_emem_arb_timing_rap2pre; /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - u_int32_t mc_emem_arb_timing_wap2pre; + uint32_t mc_emem_arb_timing_wap2pre; /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - u_int32_t mc_emem_arb_timing_r2r; + uint32_t mc_emem_arb_timing_r2r; /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - u_int32_t mc_emem_arb_timing_w2w; + uint32_t mc_emem_arb_timing_w2w; /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - u_int32_t mc_emem_arb_timing_r2w; + uint32_t mc_emem_arb_timing_r2w; /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - u_int32_t mc_emem_arb_timing_w2r; + uint32_t mc_emem_arb_timing_w2r; /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - u_int32_t mc_emem_arb_da_turns; + uint32_t mc_emem_arb_da_turns; /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - u_int32_t mc_emem_arb_da_covers; + uint32_t mc_emem_arb_da_covers; /* Specifies the value for MC_EMEM_ARB_MISC0 */ - u_int32_t mc_emem_arb_misc0; + uint32_t mc_emem_arb_misc0; /* Specifies the value for MC_EMEM_ARB_MISC1 */ - u_int32_t mc_emem_arb_misc1; + uint32_t mc_emem_arb_misc1; /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - u_int32_t mc_emem_arb_ring1_throttle; + uint32_t mc_emem_arb_ring1_throttle; /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - u_int32_t mc_emem_arb_override; + uint32_t mc_emem_arb_override; /* Specifies the value for MC_EMEM_ARB_RSV */ - u_int32_t mc_emem_arb_rsv; + uint32_t mc_emem_arb_rsv; /* Specifies the value for MC_CLKEN_OVERRIDE */ - u_int32_t mc_clken_override; + uint32_t mc_clken_override; /* End of generated code by warmboot_code_gen */ } nvboot_sdram_params; |