diff options
Diffstat (limited to 'src/t210')
| -rw-r--r-- | src/t210/nvbctlib_t210.c | 80 | ||||
| -rw-r--r-- | src/t210/nvboot_bct_t210.h | 86 | ||||
| -rw-r--r-- | src/t210/nvboot_sdram_param_t210.h | 994 |
3 files changed, 580 insertions, 580 deletions
diff --git a/src/t210/nvbctlib_t210.c b/src/t210/nvbctlib_t210.c index 1d41cd6..53d5da7 100644 --- a/src/t210/nvbctlib_t210.c +++ b/src/t210/nvbctlib_t210.c @@ -60,22 +60,22 @@ case token_bl_##x:\ case token_##id:\ if (bct == NULL) \ return -ENODATA; \ - *((u_int32_t *)data) = bct_ptr->id; \ + *((uint32_t *)data) = bct_ptr->id; \ break #define CASE_GET_CONST(id, val) \ case token_##id:\ - *((u_int32_t *)data) = val; \ + *((uint32_t *)data) = val; \ break #define CASE_GET_CONST_PREFIX(id, val_prefix) \ case token_##id:\ - *((u_int32_t *)data) = val_prefix##_##id; \ + *((uint32_t *)data) = val_prefix##_##id; \ break #define CASE_SET_NVU32(id) \ case token_##id:\ - bct_ptr->id = *((u_int32_t *)data); \ + bct_ptr->id = *((uint32_t *)data); \ break #define CASE_GET_DATA(id, size) \ @@ -123,9 +123,9 @@ parse_token t210_root_token_list[] = { int t210_set_dev_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t value) + uint32_t value) { nvboot_config_table *bct = NULL; @@ -159,9 +159,9 @@ t210_set_dev_param(build_image_context *context, int t210_get_dev_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t *value) + uint32_t *value) { nvboot_config_table *bct = NULL; @@ -193,9 +193,9 @@ t210_get_dev_param(build_image_context *context, int t210_get_sdram_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t *value) + uint32_t *value) { nvboot_sdram_params *params; nvboot_config_table *bct = NULL; @@ -1100,9 +1100,9 @@ t210_get_sdram_param(build_image_context *context, int t210_set_sdram_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t value) + uint32_t value) { nvboot_sdram_params *params; nvboot_config_table *bct = NULL; @@ -2009,10 +2009,10 @@ t210_set_sdram_param(build_image_context *context, } int -t210_getbl_param(u_int32_t set, +t210_getbl_param(uint32_t set, parse_token id, - u_int32_t *data, - u_int8_t *bct) + uint32_t *data, + uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -2037,8 +2037,8 @@ t210_getbl_param(u_int32_t set, break; case token_rsa_pss_sig_bl: - reverse_byte_order((u_int8_t *)data, - (const u_int8_t *)&bct_ptr->bootloader[set].signature.rsa_pss_sig, + reverse_byte_order((uint8_t *)data, + (const uint8_t *)&bct_ptr->bootloader[set].signature.rsa_pss_sig, sizeof(nvboot_rsa_pss_sig)); break; @@ -2050,10 +2050,10 @@ t210_getbl_param(u_int32_t set, } int -t210_setbl_param(u_int32_t set, +t210_setbl_param(uint32_t set, parse_token id, - u_int32_t *data, - u_int8_t *bct) + uint32_t *data, + uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -2085,7 +2085,7 @@ t210_setbl_param(u_int32_t set, } int -t210_bct_get_value(parse_token id, void *data, u_int8_t *bct) +t210_bct_get_value(parse_token id, void *data, uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; nvboot_config_table samplebct; /* Used for computing offsets. */ @@ -2114,13 +2114,13 @@ t210_bct_get_value(parse_token id, void *data, u_int8_t *bct) case token_block_size: if (bct == NULL) return -ENODATA; - *((u_int32_t *)data) = 1 << bct_ptr->block_size_log2; + *((uint32_t *)data) = 1 << bct_ptr->block_size_log2; break; case token_page_size: if (bct == NULL) return -ENODATA; - *((u_int32_t *)data) = 1 << bct_ptr->page_size_log2; + *((uint32_t *)data) = 1 << bct_ptr->page_size_log2; break; /* @@ -2139,37 +2139,37 @@ t210_bct_get_value(parse_token id, void *data, u_int8_t *bct) break; case token_rsa_key_modulus: - reverse_byte_order(data, (const u_int8_t *)&bct_ptr->key, + reverse_byte_order(data, (const uint8_t *)&bct_ptr->key, sizeof(nvboot_rsa_key_modulus)); break; case token_rsa_pss_sig_bct: reverse_byte_order(data, - (const u_int8_t *)&bct_ptr->signature.rsa_pss_sig, + (const uint8_t *)&bct_ptr->signature.rsa_pss_sig, sizeof(nvboot_rsa_pss_sig)); break; case token_reserved_offset: - *((u_int32_t *)data) = (u_int8_t *)&(samplebct.reserved) - - (u_int8_t *)&samplebct; + *((uint32_t *)data) = (uint8_t *)&(samplebct.reserved) + - (uint8_t *)&samplebct; break; case token_bct_size: - *((u_int32_t *)data) = sizeof(nvboot_config_table); + *((uint32_t *)data) = sizeof(nvboot_config_table); break; CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); case token_crypto_offset: /* Offset to region in BCT to encrypt & sign */ - *((u_int32_t *)data) = (u_int8_t *)&(samplebct.random_aes_blk) - - (u_int8_t *)&samplebct; + *((uint32_t *)data) = (uint8_t *)&(samplebct.random_aes_blk) + - (uint8_t *)&samplebct; break; case token_crypto_length: /* size of region in BCT to encrypt & sign */ - *((u_int32_t *)data) = (u_int8_t *)bct_ptr + sizeof(nvboot_config_table) - - (u_int8_t *)&(bct_ptr->random_aes_blk); + *((uint32_t *)data) = (uint8_t *)bct_ptr + sizeof(nvboot_config_table) + - (uint8_t *)&(bct_ptr->random_aes_blk); break; CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); @@ -2218,7 +2218,7 @@ t210_bct_get_value_size(parse_token id) } int -t210_bct_set_value(parse_token id, void *data, u_int8_t *bct) +t210_bct_set_value(parse_token id, void *data, uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -2243,7 +2243,7 @@ t210_bct_set_value(parse_token id, void *data, u_int8_t *bct) break; case token_rsa_key_modulus: - reverse_byte_order((u_int8_t *)&bct_ptr->key, data, + reverse_byte_order((uint8_t *)&bct_ptr->key, data, sizeof(nvboot_rsa_key_modulus)); break; @@ -2253,12 +2253,12 @@ t210_bct_set_value(parse_token id, void *data, u_int8_t *bct) * of bootloader being built in. */ reverse_byte_order( - (u_int8_t *)&bct_ptr->bootloader[0].signature.rsa_pss_sig, + (uint8_t *)&bct_ptr->bootloader[0].signature.rsa_pss_sig, data, sizeof(nvboot_rsa_pss_sig)); break; case token_rsa_pss_sig_bct: - reverse_byte_order((u_int8_t *)&bct_ptr->signature.rsa_pss_sig, + reverse_byte_order((uint8_t *)&bct_ptr->signature.rsa_pss_sig, data, sizeof(nvboot_rsa_pss_sig)); break; @@ -2271,9 +2271,9 @@ t210_bct_set_value(parse_token id, void *data, u_int8_t *bct) int t210_bct_set_data(parse_token id, - u_int8_t *data, - u_int32_t length, - u_int8_t *bct) + uint8_t *data, + uint32_t length, + uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -2313,7 +2313,7 @@ int t210_bct_token_supported(parse_token token) void t210_init_bad_block_table(build_image_context *context) { - u_int32_t bytes_per_entry; + uint32_t bytes_per_entry; nvboot_badblock_table *table; nvboot_config_table *bct; diff --git a/src/t210/nvboot_bct_t210.h b/src/t210/nvboot_bct_t210.h index 90841f6..0946395 100644 --- a/src/t210/nvboot_bct_t210.h +++ b/src/t210/nvboot_bct_t210.h @@ -110,7 +110,7 @@ enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; * Defines the storage for a hash value (128 bits). */ typedef struct nvboot_hash_rec { - u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; } nvboot_hash; /* @@ -119,7 +119,7 @@ typedef struct nvboot_hash_rec { */ typedef struct nvboot_rsa_key_modulus_rec { /* The modulus size is 2048-bits. */ - u_int32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; + uint32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; } nvboot_rsa_key_modulus; typedef struct nvboot_rsa_pss_sig_rec { @@ -128,7 +128,7 @@ typedef struct nvboot_rsa_pss_sig_rec { * length in octets of the RSA modulus. * In our case, it's 2048-bits. */ - u_int32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; + uint32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; } nvboot_rsa_pss_sig; typedef struct nvboot_object_signature_rec { @@ -146,10 +146,10 @@ typedef struct nvboot_object_signature_rec { } nvboot_object_signature; typedef struct nvboot_ecid_rec { - u_int32_t ecid_0; - u_int32_t ecid_1; - u_int32_t ecid_2; - u_int32_t ecid_3; + uint32_t ecid_0; + uint32_t ecid_1; + uint32_t ecid_2; + uint32_t ecid_3; } nvboot_ecid; /* Defines various data widths supported. */ @@ -186,7 +186,7 @@ typedef struct nvboot_sdmmc_params_rec { * which is PLLP running at 216MHz. If it is set to 9, then the SDMMC * controller runs at 216/9 = 24MHz. */ - u_int8_t clock_divider; + uint8_t clock_divider; /* Specifies the data bus width. Supported data widths are 4/8 bits. */ nvboot_sdmmc_data_width data_width; @@ -197,10 +197,10 @@ typedef struct nvboot_sdmmc_params_rec { * supported within the power class range (0 to Max) if the selected * data width cannot be used at the chosen clock frequency. */ - u_int8_t max_power_class_supported; + uint8_t max_power_class_supported; /* Specifies the max page size supported by driver */ - u_int8_t multi_page_support; + uint8_t multi_page_support; } nvboot_sdmmc_params; typedef enum { @@ -221,7 +221,7 @@ typedef struct nvboot_spiflash_params_rec { /** * Specifies the clock source to use. */ - u_int32_t clock_source; + uint32_t clock_source; /** * Specifes the clock divider to use. @@ -233,24 +233,24 @@ typedef struct nvboot_spiflash_params_rec { * FAST_READ at 40MHz: 11 * FAST_READ at 50MHz: 9 */ - u_int8_t clock_divider; + uint8_t clock_divider; /** * Specifies the type of command for read operations. * NV_FALSE specifies a NORMAL_READ Command * NV_TRUE specifies a FAST_READ Command */ - u_int8_t read_command_type_fast; + uint8_t read_command_type_fast; /* 0 = 2k page size, 1 = 16K page size */ - u_int8_t page_size_2k_or_16k; + uint8_t page_size_2k_or_16k; } nvboot_spiflash_params; /** * Defines the union of the parameters required by each device. */ typedef union { - u_int8_t size[64]; + uint8_t size[64]; /* Specifies optimized parameters for eMMC and eSD */ nvboot_sdmmc_params sdmmc_params; /* Specifies optimized parameters for SPI NOR */ @@ -286,13 +286,13 @@ typedef enum { * the device. */ typedef struct nv_bootloader_info_rec { - u_int32_t version; - u_int32_t start_blk; - u_int32_t start_page; - u_int32_t length; - u_int32_t load_addr; - u_int32_t entry_point; - u_int32_t attribute; + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; /* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */ nvboot_object_signature signature; @@ -302,15 +302,15 @@ typedef struct nv_bootloader_info_rec { * Defines the bad block table structure stored in the BCT. */ typedef struct nvboot_badblock_table_rec { - u_int32_t entries_used; - u_int8_t virtual_blk_size_log2; - u_int8_t block_size_log2; - u_int8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; /* * Add a reserved field as padding to make the bad block table structure * a multiple of 16 bytes (AES block size). */ - u_int8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; + uint8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; } nvboot_badblock_table; enum {NVBOOT_SE_AES_KEY256_LENGTH_BYTES = 32}; @@ -335,35 +335,35 @@ typedef struct nvboot_config_table_rec { * This field must match SecProvisioningKeyNum_Secure to be a valid * BCT for use in the Factory Secure Provisioning mode. */ - u_int32_t secure_provisioning_key_number_insecure; /* 420 */ + uint32_t secure_provisioning_key_number_insecure; /* 420 */ /** * A 256-bit AES key encrypted by a reserved 256-bit AES "key wrap" * key. Only used in Factory Secure Provisioning mode. */ - u_int8_t aes_key[NVBOOT_SE_AES_KEY256_LENGTH_BYTES]; /* 424 */ + uint8_t aes_key[NVBOOT_SE_AES_KEY256_LENGTH_BYTES]; /* 424 */ - u_int8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; /* 444 */ - u_int32_t odm_data; /* 508 */ - u_int32_t reserved1; + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; /* 444 */ + uint32_t odm_data; /* 508 */ + uint32_t reserved1; /* START OF SIGNED SECTION OF THE BCT */ nvboot_hash random_aes_blk; /* 0x510 */ nvboot_ecid unique_chip_id; /* 0x520 */ - u_int32_t boot_data_version; /* 0x530 */ - u_int32_t block_size_log2; - u_int32_t page_size_log2; - u_int32_t partition_size; - u_int32_t num_param_sets; + uint32_t boot_data_version; /* 0x530 */ + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; - u_int32_t num_sdram_sets; /* 0x588 */ + uint32_t num_sdram_sets; /* 0x588 */ nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; /* 0x58c */ - u_int32_t bootloader_used; /* 0x232c */ + uint32_t bootloader_used; /* 0x232c */ nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; /* 0x2330 */ - u_int8_t enable_fail_back; + uint8_t enable_fail_back; /** * Specifies which debug features to be enabled or disabled. @@ -377,7 +377,7 @@ typedef struct nvboot_config_table_rec { * DEVICEEN - bit 1 * JTAG_ENABLE - bit 0 */ - u_int32_t secure_debug_control; + uint32_t secure_debug_control; /** * Specifies the factory secure provisioning key number to use. @@ -399,8 +399,8 @@ typedef struct nvboot_config_table_rec { * * This key number must match SecProvisioningKeyNum_Insecure. */ - u_int32_t secure_provisioning_key_number_secure; + uint32_t secure_provisioning_key_number_secure; - u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; } nvboot_config_table; #endif /* #ifndef INCLUDED_NVBOOT_BCT_T210_H */ diff --git a/src/t210/nvboot_sdram_param_t210.h b/src/t210/nvboot_sdram_param_t210.h index c4671e4..67ae9f6 100644 --- a/src/t210/nvboot_sdram_param_t210.h +++ b/src/t210/nvboot_sdram_param_t210.h @@ -66,470 +66,470 @@ typedef struct nvboot_sdram_params_rec { /* MC/EMC clock source configuration */ /* Specifies the M value for PllM */ - u_int32_t pllm_input_divider; + uint32_t pllm_input_divider; /* Specifies the N value for PllM */ - u_int32_t pllm_feedback_divider; + uint32_t pllm_feedback_divider; /* Specifies the time to wait for PLLM to lock (in microseconds) */ - u_int32_t pllm_stable_time; + uint32_t pllm_stable_time; /* Specifies misc. control bits */ - u_int32_t pllm_setup_control; + uint32_t pllm_setup_control; /* Specifies the P value for PLLM */ - u_int32_t pllm_post_divider; + uint32_t pllm_post_divider; /* Specifies value for Charge Pump Gain Control */ - u_int32_t pllm_kcp; + uint32_t pllm_kcp; /* Specifies VCO gain */ - u_int32_t pllm_kvco; + uint32_t pllm_kvco; /* Spare BCT param */ - u_int32_t emc_bct_spare0; + uint32_t emc_bct_spare0; /* Spare BCT param */ - u_int32_t emc_bct_spare1; + uint32_t emc_bct_spare1; /* Spare BCT param */ - u_int32_t emc_bct_spare2; + uint32_t emc_bct_spare2; /* Spare BCT param */ - u_int32_t emc_bct_spare3; + uint32_t emc_bct_spare3; /* Spare BCT param */ - u_int32_t emc_bct_spare4; + uint32_t emc_bct_spare4; /* Spare BCT param */ - u_int32_t emc_bct_spare5; + uint32_t emc_bct_spare5; /* Spare BCT param */ - u_int32_t emc_bct_spare6; + uint32_t emc_bct_spare6; /* Spare BCT param */ - u_int32_t emc_bct_spare7; + uint32_t emc_bct_spare7; /* Spare BCT param */ - u_int32_t emc_bct_spare8; + uint32_t emc_bct_spare8; /* Spare BCT param */ - u_int32_t emc_bct_spare9; + uint32_t emc_bct_spare9; /* Spare BCT param */ - u_int32_t emc_bct_spare10; + uint32_t emc_bct_spare10; /* Spare BCT param */ - u_int32_t emc_bct_spare11; + uint32_t emc_bct_spare11; /* Spare BCT param */ - u_int32_t emc_bct_spare12; + uint32_t emc_bct_spare12; /* Spare BCT param */ - u_int32_t emc_bct_spare13; + uint32_t emc_bct_spare13; /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - u_int32_t emc_clock_source; - u_int32_t emc_clock_source_dll; + uint32_t emc_clock_source; + uint32_t emc_clock_source_dll; /* Defines possible override for PLLLM_MISC2 */ - u_int32_t clk_rst_pllm_misc20_override; + uint32_t clk_rst_pllm_misc20_override; /* enables override for PLLLM_MISC2 */ - u_int32_t clk_rst_pllm_misc20_override_enable; + uint32_t clk_rst_pllm_misc20_override_enable; /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ - u_int32_t clear_clock2_mc1; + uint32_t clear_clock2_mc1; /* Auto-calibration of EMC pads */ /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - u_int32_t emc_auto_cal_interval; + uint32_t emc_auto_cal_interval; /* * Specifies the value for EMC_AUTO_CAL_CONFIG * Note: Trigger bits are set by the SDRAM code. */ - u_int32_t emc_auto_cal_config; + uint32_t emc_auto_cal_config; /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - u_int32_t emc_auto_cal_config2; + uint32_t emc_auto_cal_config2; /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - u_int32_t emc_auto_cal_config3; + uint32_t emc_auto_cal_config3; - u_int32_t emc_auto_cal_config4; - u_int32_t emc_auto_cal_config5; - u_int32_t emc_auto_cal_config6; - u_int32_t emc_auto_cal_config7; - u_int32_t emc_auto_cal_config8; + uint32_t emc_auto_cal_config4; + uint32_t emc_auto_cal_config5; + uint32_t emc_auto_cal_config6; + uint32_t emc_auto_cal_config7; + uint32_t emc_auto_cal_config8; /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ - u_int32_t emc_auto_cal_vref_sel0; - u_int32_t emc_auto_cal_vref_sel1; + uint32_t emc_auto_cal_vref_sel0; + uint32_t emc_auto_cal_vref_sel1; /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ - u_int32_t emc_auto_cal_channel; + uint32_t emc_auto_cal_channel; /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ - u_int32_t emc_pmacro_auto_cal_cfg0; - u_int32_t emc_pmacro_auto_cal_cfg1; - u_int32_t emc_pmacro_auto_cal_cfg2; + uint32_t emc_pmacro_auto_cal_cfg0; + uint32_t emc_pmacro_auto_cal_cfg1; + uint32_t emc_pmacro_auto_cal_cfg2; - u_int32_t emc_pmacro_rx_term; - u_int32_t emc_pmacro_dq_tx_drive; - u_int32_t emc_pmacro_ca_tx_drive; - u_int32_t emc_pmacro_cmd_tx_drive; - u_int32_t emc_pmacro_auto_cal_common; - u_int32_t emc_pmacro_zcrtl; + uint32_t emc_pmacro_rx_term; + uint32_t emc_pmacro_dq_tx_drive; + uint32_t emc_pmacro_ca_tx_drive; + uint32_t emc_pmacro_cmd_tx_drive; + uint32_t emc_pmacro_auto_cal_common; + uint32_t emc_pmacro_zcrtl; /* * Specifies the time for the calibration * to stabilize (in microseconds) */ - u_int32_t emc_auto_cal_wait; + uint32_t emc_auto_cal_wait; - u_int32_t emc_xm2_comp_pad_ctrl; - u_int32_t emc_xm2_comp_pad_ctrl2; - u_int32_t emc_xm2_comp_pad_ctrl3; + uint32_t emc_xm2_comp_pad_ctrl; + uint32_t emc_xm2_comp_pad_ctrl2; + uint32_t emc_xm2_comp_pad_ctrl3; /* * DRAM size information * Specifies the value for EMC_ADR_CFG */ - u_int32_t emc_adr_cfg; + uint32_t emc_adr_cfg; /* * Specifies the time to wait after asserting pin * CKE (in microseconds) */ - u_int32_t emc_pin_program_wait; + uint32_t emc_pin_program_wait; /* Specifies the extra delay before/after pin RESET/CKE command */ - u_int32_t emc_pin_extra_wait; + uint32_t emc_pin_extra_wait; - u_int32_t emc_pin_gpio_enable; - u_int32_t emc_pin_gpio; + uint32_t emc_pin_gpio_enable; + uint32_t emc_pin_gpio; /* * Specifies the extra delay after the first writing * of EMC_TIMING_CONTROL */ - u_int32_t emc_timing_control_wait; + uint32_t emc_timing_control_wait; /* Timing parameters required for the SDRAM */ /* Specifies the value for EMC_RC */ - u_int32_t emc_rc; + uint32_t emc_rc; /* Specifies the value for EMC_RFC */ - u_int32_t emc_rfc; + uint32_t emc_rfc; - u_int32_t emc_rfc_pb; - u_int32_t emc_ref_ctrl2; + uint32_t emc_rfc_pb; + uint32_t emc_ref_ctrl2; /* Specifies the value for EMC_RFC_SLR */ - u_int32_t emc_rfc_slr; + uint32_t emc_rfc_slr; /* Specifies the value for EMC_RAS */ - u_int32_t emc_ras; + uint32_t emc_ras; /* Specifies the value for EMC_RP */ - u_int32_t emc_rp; + uint32_t emc_rp; /* Specifies the value for EMC_R2R */ - u_int32_t emc_r2r; + uint32_t emc_r2r; /* Specifies the value for EMC_W2W */ - u_int32_t emc_w2w; + uint32_t emc_w2w; /* Specifies the value for EMC_R2W */ - u_int32_t emc_r2w; + uint32_t emc_r2w; /* Specifies the value for EMC_W2R */ - u_int32_t emc_w2r; + uint32_t emc_w2r; /* Specifies the value for EMC_R2P */ - u_int32_t emc_r2p; + uint32_t emc_r2p; /* Specifies the value for EMC_W2P */ - u_int32_t emc_w2p; + uint32_t emc_w2p; /* Specifies the value for EMC_RD_RCD */ - u_int32_t emc_tppd; - u_int32_t emc_ccdmw; + uint32_t emc_tppd; + uint32_t emc_ccdmw; - u_int32_t emc_rd_rcd; + uint32_t emc_rd_rcd; /* Specifies the value for EMC_WR_RCD */ - u_int32_t emc_wr_rcd; + uint32_t emc_wr_rcd; /* Specifies the value for EMC_RRD */ - u_int32_t emc_rrd; + uint32_t emc_rrd; /* Specifies the value for EMC_REXT */ - u_int32_t emc_rext; + uint32_t emc_rext; /* Specifies the value for EMC_WEXT */ - u_int32_t emc_wext; + uint32_t emc_wext; /* Specifies the value for EMC_WDV */ - u_int32_t emc_wdv; + uint32_t emc_wdv; - u_int32_t emc_wdv_chk; - u_int32_t emc_wsv; - u_int32_t emc_wev; + uint32_t emc_wdv_chk; + uint32_t emc_wsv; + uint32_t emc_wev; /* Specifies the value for EMC_WDV_MASK */ - u_int32_t emc_wdv_mask; + uint32_t emc_wdv_mask; - u_int32_t emc_ws_duration; - u_int32_t emc_we_duration; + uint32_t emc_ws_duration; + uint32_t emc_we_duration; /* Specifies the value for EMC_QUSE */ - u_int32_t emc_quse; + uint32_t emc_quse; /* Specifies the value for EMC_QUSE_WIDTH */ - u_int32_t emc_quse_width; + uint32_t emc_quse_width; /* Specifies the value for EMC_IBDLY */ - u_int32_t emc_ibdly; + uint32_t emc_ibdly; - u_int32_t emc_obdly; + uint32_t emc_obdly; /* Specifies the value for EMC_EINPUT */ - u_int32_t emc_einput; + uint32_t emc_einput; /* Specifies the value for EMC_EINPUT_DURATION */ - u_int32_t emc_einput_duration; + uint32_t emc_einput_duration; /* Specifies the value for EMC_PUTERM_EXTRA */ - u_int32_t emc_puterm_extra; + uint32_t emc_puterm_extra; /* Specifies the value for EMC_PUTERM_WIDTH */ - u_int32_t emc_puterm_width; + uint32_t emc_puterm_width; - u_int32_t emc_qrst; - u_int32_t emc_qsafe; - u_int32_t emc_rdv; - u_int32_t emc_rdv_mask; + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; - u_int32_t emc_rdv_early; - u_int32_t emc_rdv_early_mask; + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; /* Specifies the value for EMC_QPOP */ - u_int32_t emc_qpop; + uint32_t emc_qpop; /* Specifies the value for EMC_REFRESH */ - u_int32_t emc_refresh; + uint32_t emc_refresh; /* Specifies the value for EMC_BURST_REFRESH_NUM */ - u_int32_t emc_burst_refresh_num; + uint32_t emc_burst_refresh_num; /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - u_int32_t emc_prerefresh_req_cnt; + uint32_t emc_prerefresh_req_cnt; /* Specifies the value for EMC_PDEX2WR */ - u_int32_t emc_pdex2wr; + uint32_t emc_pdex2wr; /* Specifies the value for EMC_PDEX2RD */ - u_int32_t emc_pdex2rd; + uint32_t emc_pdex2rd; /* Specifies the value for EMC_PCHG2PDEN */ - u_int32_t emc_pchg2pden; + uint32_t emc_pchg2pden; /* Specifies the value for EMC_ACT2PDEN */ - u_int32_t emc_act2pden; + uint32_t emc_act2pden; /* Specifies the value for EMC_AR2PDEN */ - u_int32_t emc_ar2pden; + uint32_t emc_ar2pden; /* Specifies the value for EMC_RW2PDEN */ - u_int32_t emc_rw2pden; + uint32_t emc_rw2pden; - u_int32_t emc_cke2pden; - u_int32_t emc_pdex2che; - u_int32_t emc_pdex2mrr; + uint32_t emc_cke2pden; + uint32_t emc_pdex2che; + uint32_t emc_pdex2mrr; /* Specifies the value for EMC_TXSR */ - u_int32_t emc_txsr; + uint32_t emc_txsr; /* Specifies the value for EMC_TXSRDLL */ - u_int32_t emc_txsr_dll; + uint32_t emc_txsr_dll; /* Specifies the value for EMC_TCKE */ - u_int32_t emc_tcke; + uint32_t emc_tcke; /* Specifies the value for EMC_TCKESR */ - u_int32_t emc_tckesr; + uint32_t emc_tckesr; /* Specifies the value for EMC_TPD */ - u_int32_t emc_tpd; + uint32_t emc_tpd; /* Specifies the value for EMC_TFAW */ - u_int32_t emc_tfaw; + uint32_t emc_tfaw; /* Specifies the value for EMC_TRPAB */ - u_int32_t emc_trpab; + uint32_t emc_trpab; /* Specifies the value for EMC_TCLKSTABLE */ - u_int32_t emc_tclkstable; + uint32_t emc_tclkstable; /* Specifies the value for EMC_TCLKSTOP */ - u_int32_t emc_tclkstop; + uint32_t emc_tclkstop; /* Specifies the value for EMC_TREFBW */ - u_int32_t emc_trefbw; + uint32_t emc_trefbw; /* FBIO configuration values */ /* Specifies the value for EMC_FBIO_CFG5 */ - u_int32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg5; /* Specifies the value for EMC_FBIO_CFG7 */ - u_int32_t emc_fbio_cfg7; - u_int32_t emc_fbio_cfg8; + uint32_t emc_fbio_cfg7; + uint32_t emc_fbio_cfg8; /* Command mapping for CMD brick 0 */ - u_int32_t emc_cmd_mapping_cmd0_0; - u_int32_t emc_cmd_mapping_cmd0_1; - u_int32_t emc_cmd_mapping_cmd0_2; - u_int32_t emc_cmd_mapping_cmd1_0; - u_int32_t emc_cmd_mapping_cmd1_1; - u_int32_t emc_cmd_mapping_cmd1_2; - u_int32_t emc_cmd_mapping_cmd2_0; - u_int32_t emc_cmd_mapping_cmd2_1; - u_int32_t emc_cmd_mapping_cmd2_2; - u_int32_t emc_cmd_mapping_cmd3_0; - u_int32_t emc_cmd_mapping_cmd3_1; - u_int32_t emc_cmd_mapping_cmd3_2; - u_int32_t emc_cmd_mapping_byte; + uint32_t emc_cmd_mapping_cmd0_0; + uint32_t emc_cmd_mapping_cmd0_1; + uint32_t emc_cmd_mapping_cmd0_2; + uint32_t emc_cmd_mapping_cmd1_0; + uint32_t emc_cmd_mapping_cmd1_1; + uint32_t emc_cmd_mapping_cmd1_2; + uint32_t emc_cmd_mapping_cmd2_0; + uint32_t emc_cmd_mapping_cmd2_1; + uint32_t emc_cmd_mapping_cmd2_2; + uint32_t emc_cmd_mapping_cmd3_0; + uint32_t emc_cmd_mapping_cmd3_1; + uint32_t emc_cmd_mapping_cmd3_2; + uint32_t emc_cmd_mapping_byte; /* Specifies the value for EMC_FBIO_SPARE */ - u_int32_t emc_fbio_spare; + uint32_t emc_fbio_spare; /* Specifies the value for EMC_CFG_RSV */ - u_int32_t emc_cfg_rsv; + uint32_t emc_cfg_rsv; /* MRS command values */ /* Specifies the value for EMC_MRS */ - u_int32_t emc_mrs; + uint32_t emc_mrs; /* Specifies the MP0 command to initialize mode registers */ - u_int32_t emc_emrs; + uint32_t emc_emrs; /* Specifies the MP2 command to initialize mode registers */ - u_int32_t emc_emrs2; + uint32_t emc_emrs2; /* Specifies the MP3 command to initialize mode registers */ - u_int32_t emc_emrs3; + uint32_t emc_emrs3; /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - u_int32_t emc_mrw1; + uint32_t emc_mrw1; /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - u_int32_t emc_mrw2; + uint32_t emc_mrw2; /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - u_int32_t emc_mrw3; + uint32_t emc_mrw3; /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - u_int32_t emc_mrw4; + uint32_t emc_mrw4; /* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */ - u_int32_t emc_mrw6; + uint32_t emc_mrw6; /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ - u_int32_t emc_mrw8; + uint32_t emc_mrw8; /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ - u_int32_t emc_mrw9; + uint32_t emc_mrw9; /* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */ - u_int32_t emc_mrw10; + uint32_t emc_mrw10; /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ - u_int32_t emc_mrw12; + uint32_t emc_mrw12; /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ - u_int32_t emc_mrw13; + uint32_t emc_mrw13; /* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */ - u_int32_t emc_mrw14; + uint32_t emc_mrw14; /* * Specifies the programming to extra LPDDR2 Mode Register * at cold boot */ - u_int32_t emc_mrw_extra; + uint32_t emc_mrw_extra; /* * Specifies the programming to extra LPDDR2 Mode Register * at warm boot */ - u_int32_t emc_warm_boot_mrw_extra; + uint32_t emc_warm_boot_mrw_extra; /* * Specify the enable of extra Mode Register programming at * warm boot */ - u_int32_t emc_warm_boot_extramode_reg_write_enable; + uint32_t emc_warm_boot_extramode_reg_write_enable; /* * Specify the enable of extra Mode Register programming at * cold boot */ - u_int32_t emc_extramode_reg_write_enable; + uint32_t emc_extramode_reg_write_enable; /* Specifies the EMC_MRW reset command value */ - u_int32_t emc_mrw_reset_command; + uint32_t emc_mrw_reset_command; /* Specifies the EMC Reset wait time (in microseconds) */ - u_int32_t emc_mrw_reset_ninit_wait; + uint32_t emc_mrw_reset_ninit_wait; /* Specifies the value for EMC_MRS_WAIT_CNT */ - u_int32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt; /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - u_int32_t emc_mrs_wait_cnt2; + uint32_t emc_mrs_wait_cnt2; /* EMC miscellaneous configurations */ /* Specifies the value for EMC_CFG */ - u_int32_t emc_cfg; + uint32_t emc_cfg; /* Specifies the value for EMC_CFG_2 */ - u_int32_t emc_cfg2; + uint32_t emc_cfg2; /* Specifies the pipe bypass controls */ - u_int32_t emc_cfg_pipe; + uint32_t emc_cfg_pipe; - u_int32_t emc_cfg_pipe_clk; - u_int32_t emc_fdpd_ctrl_cmd_no_ramp; - u_int32_t emc_cfg_update; + uint32_t emc_cfg_pipe_clk; + uint32_t emc_fdpd_ctrl_cmd_no_ramp; + uint32_t emc_cfg_update; /* Specifies the value for EMC_DBG */ - u_int32_t emc_dbg; + uint32_t emc_dbg; - u_int32_t emc_dbg_write_mux; + uint32_t emc_dbg_write_mux; /* Specifies the value for EMC_CMDQ */ - u_int32_t emc_cmd_q; + uint32_t emc_cmd_q; /* Specifies the value for EMC_MC2EMCQ */ - u_int32_t emc_mc2emc_q; + uint32_t emc_mc2emc_q; /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - u_int32_t emc_dyn_self_ref_control; + uint32_t emc_dyn_self_ref_control; /* Specifies the value for MEM_INIT_DONE */ - u_int32_t ahb_arbitration_xbar_ctrl_meminit_done; + uint32_t ahb_arbitration_xbar_ctrl_meminit_done; /* Specifies the value for EMC_CFG_DIG_DLL */ - u_int32_t emc_cfg_dig_dll; - u_int32_t emc_cfg_dig_dll_1; + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_1; /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - u_int32_t emc_cfg_dig_dll_period; + uint32_t emc_cfg_dig_dll_period; /* Specifies the value of *DEV_SELECTN of various EMC registers */ - u_int32_t emc_dev_select; + uint32_t emc_dev_select; /* Specifies the value for EMC_SEL_DPD_CTRL */ - u_int32_t emc_sel_dpd_ctrl; + uint32_t emc_sel_dpd_ctrl; /* Pads trimmer delays */ - u_int32_t emc_fdpd_ctrl_dq; - u_int32_t emc_fdpd_ctrl_cmd; - u_int32_t emc_pmacro_ib_vref_dq_0; - u_int32_t emc_pmacro_ib_vref_dq_1; - u_int32_t emc_pmacro_ib_vref_dqs_0; - u_int32_t emc_pmacro_ib_vref_dqs_1; - u_int32_t emc_pmacro_ib_rxrt; - u_int32_t emc_cfg_pipe1; - u_int32_t emc_cfg_pipe2; + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_pmacro_ib_vref_dq_0; + uint32_t emc_pmacro_ib_vref_dq_1; + uint32_t emc_pmacro_ib_vref_dqs_0; + uint32_t emc_pmacro_ib_vref_dqs_1; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe1; + uint32_t emc_cfg_pipe2; /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ - u_int32_t emc_pmacro_quse_ddll_rank0_0; - u_int32_t emc_pmacro_quse_ddll_rank0_1; - u_int32_t emc_pmacro_quse_ddll_rank0_2; - u_int32_t emc_pmacro_quse_ddll_rank0_3; - u_int32_t emc_pmacro_quse_ddll_rank0_4; - u_int32_t emc_pmacro_quse_ddll_rank0_5; - u_int32_t emc_pmacro_quse_ddll_rank1_0; - u_int32_t emc_pmacro_quse_ddll_rank1_1; - u_int32_t emc_pmacro_quse_ddll_rank1_2; - u_int32_t emc_pmacro_quse_ddll_rank1_3; - u_int32_t emc_pmacro_quse_ddll_rank1_4; - u_int32_t emc_pmacro_quse_ddll_rank1_5; - - u_int32_t emc_pmacro_ob_ddll_long_dq_rank0_0; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank0_1; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank0_2; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank0_3; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank0_4; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank0_5; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank1_0; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank1_1; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank1_2; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank1_3; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank1_4; - u_int32_t emc_pmacro_ob_ddll_long_dq_rank1_5; - - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; - u_int32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; - - u_int32_t emc_pmacro_ib_ddll_long_dqs_rank0_0; - u_int32_t emc_pmacro_ib_ddll_long_dqs_rank0_1; - u_int32_t emc_pmacro_ib_ddll_long_dqs_rank0_2; - u_int32_t emc_pmacro_ib_ddll_long_dqs_rank0_3; - u_int32_t emc_pmacro_ib_ddll_long_dqs_rank1_0; - u_int32_t emc_pmacro_ib_ddll_long_dqs_rank1_1; - u_int32_t emc_pmacro_ib_ddll_long_dqs_rank1_2; - u_int32_t emc_pmacro_ib_ddll_long_dqs_rank1_3; - - u_int32_t emc_pmacro_ddll_long_cmd_0; - u_int32_t emc_pmacro_ddll_long_cmd_1; - u_int32_t emc_pmacro_ddll_long_cmd_2; - u_int32_t emc_pmacro_ddll_long_cmd_3; - u_int32_t emc_pmacro_ddll_long_cmd_4; - u_int32_t emc_pmacro_ddll_short_cmd_0; - u_int32_t emc_pmacro_ddll_short_cmd_1; - u_int32_t emc_pmacro_ddll_short_cmd_2; + uint32_t emc_pmacro_quse_ddll_rank0_0; + uint32_t emc_pmacro_quse_ddll_rank0_1; + uint32_t emc_pmacro_quse_ddll_rank0_2; + uint32_t emc_pmacro_quse_ddll_rank0_3; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_0; + uint32_t emc_pmacro_quse_ddll_rank1_1; + uint32_t emc_pmacro_quse_ddll_rank1_2; + uint32_t emc_pmacro_quse_ddll_rank1_3; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3; + + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; /* * Specifies the delay after asserting CKE pin during a WarmBoot0 * sequence (in microseconds) */ - u_int32_t warm_boot_wait; + uint32_t warm_boot_wait; /* Specifies the value for EMC_ODT_WRITE */ - u_int32_t emc_odt_write; + uint32_t emc_odt_write; /* Periodic ZQ calibration */ @@ -537,416 +537,416 @@ typedef struct nvboot_sdram_params_rec { * Specifies the value for EMC_ZCAL_INTERVAL * Value 0 disables ZQ calibration */ - u_int32_t emc_zcal_interval; + uint32_t emc_zcal_interval; /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - u_int32_t emc_zcal_wait_cnt; + uint32_t emc_zcal_wait_cnt; /* Specifies the value for EMC_ZCAL_MRW_CMD */ - u_int32_t emc_zcal_mrw_cmd; + uint32_t emc_zcal_mrw_cmd; /* DRAM initialization sequence flow control */ /* Specifies the MRS command value for resetting DLL */ - u_int32_t emc_mrs_reset_dll; + uint32_t emc_mrs_reset_dll; /* Specifies the command for ZQ initialization of device 0 */ - u_int32_t emc_zcal_init_dev0; + uint32_t emc_zcal_init_dev0; /* Specifies the command for ZQ initialization of device 1 */ - u_int32_t emc_zcal_init_dev1; + uint32_t emc_zcal_init_dev1; /* * Specifies the wait time after programming a ZQ initialization * command (in microseconds) */ - u_int32_t emc_zcal_init_wait; + uint32_t emc_zcal_init_wait; /* * Specifies the enable for ZQ calibration at cold boot [bit 0] * and warm boot [bit 1] */ - u_int32_t emc_zcal_warm_cold_boot_enables; + uint32_t emc_zcal_warm_cold_boot_enables; /* * Specifies the MRW command to LPDDR2 for ZQ calibration * on warmboot */ /* Is issued to both devices separately */ - u_int32_t emc_mrw_lpddr2zcal_warm_boot; + uint32_t emc_mrw_lpddr2zcal_warm_boot; /* * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot * Is issued to both devices separately */ - u_int32_t emc_zqcal_ddr3_warm_boot; + uint32_t emc_zqcal_ddr3_warm_boot; - u_int32_t emc_zqcal_lpddr4_warm_boot; + uint32_t emc_zqcal_lpddr4_warm_boot; /* * Specifies the wait time for ZQ calibration on warmboot * (in microseconds) */ - u_int32_t emc_zcal_warm_boot_wait; + uint32_t emc_zcal_warm_boot_wait; /* * Specifies the enable for DRAM Mode Register programming * at warm boot */ - u_int32_t emc_mrs_warm_boot_enable; + uint32_t emc_mrs_warm_boot_enable; /* * Specifies the wait time after sending an MRS DLL reset command * in microseconds) */ - u_int32_t emc_mrs_reset_dll_wait; + uint32_t emc_mrs_reset_dll_wait; /* Specifies the extra MRS command to initialize mode registers */ - u_int32_t emc_mrs_extra; + uint32_t emc_mrs_extra; /* Specifies the extra MRS command at warm boot */ - u_int32_t emc_warm_boot_mrs_extra; + uint32_t emc_warm_boot_mrs_extra; /* Specifies the EMRS command to enable the DDR2 DLL */ - u_int32_t emc_emrs_ddr2_dll_enable; + uint32_t emc_emrs_ddr2_dll_enable; /* Specifies the MRS command to reset the DDR2 DLL */ - u_int32_t emc_mrs_ddr2_dll_reset; + uint32_t emc_mrs_ddr2_dll_reset; /* Specifies the EMRS command to set OCD calibration */ - u_int32_t emc_emrs_ddr2_ocd_calib; + uint32_t emc_emrs_ddr2_ocd_calib; /* * Specifies the wait between initializing DDR and setting OCD * calibration (in microseconds) */ - u_int32_t emc_ddr2_wait; + uint32_t emc_ddr2_wait; /* Specifies the value for EMC_CLKEN_OVERRIDE */ - u_int32_t emc_clken_override; + uint32_t emc_clken_override; /* * Specifies LOG2 of the extra refresh numbers after booting * Program 0 to disable */ - u_int32_t emc_extra_refresh_num; + uint32_t emc_extra_refresh_num; /* Specifies the master override for all EMC clocks */ - u_int32_t emc_clken_override_allwarm_boot; + uint32_t emc_clken_override_allwarm_boot; /* Specifies the master override for all MC clocks */ - u_int32_t mc_clken_override_allwarm_boot; + uint32_t mc_clken_override_allwarm_boot; /* Specifies digital dll period, choosing between 4 to 64 ms */ - u_int32_t emc_cfg_dig_dll_period_warm_boot; + uint32_t emc_cfg_dig_dll_period_warm_boot; /* Pad controls */ /* Specifies the value for PMC_VDDP_SEL */ - u_int32_t pmc_vddp_sel; + uint32_t pmc_vddp_sel; /* Specifies the wait time after programming PMC_VDDP_SEL */ - u_int32_t pmc_vddp_sel_wait; + uint32_t pmc_vddp_sel_wait; /* Specifies the value for PMC_DDR_PWR */ - u_int32_t pmc_ddr_pwr; + uint32_t pmc_ddr_pwr; /* Specifies the value for PMC_DDR_CFG */ - u_int32_t pmc_ddr_cfg; + uint32_t pmc_ddr_cfg; /* Specifies the value for PMC_IO_DPD3_REQ */ - u_int32_t pmc_io_dpd3_req; + uint32_t pmc_io_dpd3_req; /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - u_int32_t pmc_io_dpd3_req_wait; + uint32_t pmc_io_dpd3_req_wait; - u_int32_t pmc_io_dpd4_req_wait; + uint32_t pmc_io_dpd4_req_wait; /* Specifies the value for PMC_REG_SHORT */ - u_int32_t pmc_reg_short; + uint32_t pmc_reg_short; /* Specifies the value for PMC_NO_IOPOWER */ - u_int32_t pmc_no_io_power; + uint32_t pmc_no_io_power; - u_int32_t pmc_ddr_ctrl_wait; - u_int32_t pmc_ddr_ctrl; + uint32_t pmc_ddr_ctrl_wait; + uint32_t pmc_ddr_ctrl; /* Specifies the value for EMC_ACPD_CONTROL */ - u_int32_t emc_acpd_control; + uint32_t emc_acpd_control; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - u_int32_t emc_swizzle_rank0_byte0; + uint32_t emc_swizzle_rank0_byte0; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - u_int32_t emc_swizzle_rank0_byte1; + uint32_t emc_swizzle_rank0_byte1; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - u_int32_t emc_swizzle_rank0_byte2; + uint32_t emc_swizzle_rank0_byte2; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - u_int32_t emc_swizzle_rank0_byte3; + uint32_t emc_swizzle_rank0_byte3; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - u_int32_t emc_swizzle_rank1_byte0; + uint32_t emc_swizzle_rank1_byte0; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - u_int32_t emc_swizzle_rank1_byte1; + uint32_t emc_swizzle_rank1_byte1; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - u_int32_t emc_swizzle_rank1_byte2; + uint32_t emc_swizzle_rank1_byte2; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - u_int32_t emc_swizzle_rank1_byte3; + uint32_t emc_swizzle_rank1_byte3; /* Specifies the value for EMC_TXDSRVTTGEN */ - u_int32_t emc_txdsrvttgen; + uint32_t emc_txdsrvttgen; /* Specifies the value for EMC_DATA_BRLSHFT_0 */ - u_int32_t emc_data_brlshft0; - u_int32_t emc_data_brlshft1; - - u_int32_t emc_dqs_brlshft0; - u_int32_t emc_dqs_brlshft1; - - u_int32_t emc_cmd_brlshft0; - u_int32_t emc_cmd_brlshft1; - u_int32_t emc_cmd_brlshft2; - u_int32_t emc_cmd_brlshft3; - - u_int32_t emc_quse_brlshft0; - u_int32_t emc_quse_brlshft1; - u_int32_t emc_quse_brlshft2; - u_int32_t emc_quse_brlshft3; - - u_int32_t emc_dll_cfg0; - u_int32_t emc_dll_cfg1; - - u_int32_t emc_pmc_scratch1; - u_int32_t emc_pmc_scratch2; - u_int32_t emc_pmc_scratch3; - - u_int32_t emc_pmacro_pad_cfg_ctrl; - - u_int32_t emc_pmacro_vttgen_ctrl0; - u_int32_t emc_pmacro_vttgen_ctrl1; - u_int32_t emc_pmacro_vttgen_ctrl2; - - u_int32_t emc_pmacro_brick_ctrl_rfu1; - u_int32_t emc_pmacro_cmd_brick_ctrl_fdpd; - u_int32_t emc_pmacro_brick_ctrl_rfu2; - u_int32_t emc_pmacro_data_brick_ctrl_fdpd; - u_int32_t emc_pmacro_bg_bias_ctrl0; - u_int32_t emc_pmacro_data_pad_rx_ctrl; - u_int32_t emc_pmacro_cmd_pad_rx_ctrl; - u_int32_t emc_pmacro_data_rx_term_mode; - u_int32_t emc_pmacro_cmd_rx_term_mode; - u_int32_t emc_pmacro_data_pad_tx_ctrl; - u_int32_t emc_pmacro_common_pad_tx_ctrl; - u_int32_t emc_pmacro_cmd_pad_tx_ctrl; - u_int32_t emc_cfg3; - - u_int32_t emc_pmacro_tx_pwrd0; - u_int32_t emc_pmacro_tx_pwrd1; - u_int32_t emc_pmacro_tx_pwrd2; - u_int32_t emc_pmacro_tx_pwrd3; - u_int32_t emc_pmacro_tx_pwrd4; - u_int32_t emc_pmacro_tx_pwrd5; - - u_int32_t emc_config_sample_delay; - - u_int32_t emc_pmacro_brick_mapping0; - u_int32_t emc_pmacro_brick_mapping1; - u_int32_t emc_pmacro_brick_mapping2; - - u_int32_t emc_pmacro_tx_sel_clk_src0; - u_int32_t emc_pmacro_tx_sel_clk_src1; - u_int32_t emc_pmacro_tx_sel_clk_src2; - u_int32_t emc_pmacro_tx_sel_clk_src3; - u_int32_t emc_pmacro_tx_sel_clk_src4; - u_int32_t emc_pmacro_tx_sel_clk_src5; - - u_int32_t emc_pmacro_ddll_bypass; - - u_int32_t emc_pmacro_ddll_pwrd0; - u_int32_t emc_pmacro_ddll_pwrd1; - u_int32_t emc_pmacro_ddll_pwrd2; - - u_int32_t emc_pmacro_cmd_ctrl0; - u_int32_t emc_pmacro_cmd_ctrl1; - u_int32_t emc_pmacro_cmd_ctrl2; + uint32_t emc_data_brlshft0; + uint32_t emc_data_brlshft1; + + uint32_t emc_dqs_brlshft0; + uint32_t emc_dqs_brlshft1; + + uint32_t emc_cmd_brlshft0; + uint32_t emc_cmd_brlshft1; + uint32_t emc_cmd_brlshft2; + uint32_t emc_cmd_brlshft3; + + uint32_t emc_quse_brlshft0; + uint32_t emc_quse_brlshft1; + uint32_t emc_quse_brlshft2; + uint32_t emc_quse_brlshft3; + + uint32_t emc_dll_cfg0; + uint32_t emc_dll_cfg1; + + uint32_t emc_pmc_scratch1; + uint32_t emc_pmc_scratch2; + uint32_t emc_pmc_scratch3; + + uint32_t emc_pmacro_pad_cfg_ctrl; + + uint32_t emc_pmacro_vttgen_ctrl0; + uint32_t emc_pmacro_vttgen_ctrl1; + uint32_t emc_pmacro_vttgen_ctrl2; + + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl0; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_common_pad_tx_ctrl; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_cfg3; + + uint32_t emc_pmacro_tx_pwrd0; + uint32_t emc_pmacro_tx_pwrd1; + uint32_t emc_pmacro_tx_pwrd2; + uint32_t emc_pmacro_tx_pwrd3; + uint32_t emc_pmacro_tx_pwrd4; + uint32_t emc_pmacro_tx_pwrd5; + + uint32_t emc_config_sample_delay; + + uint32_t emc_pmacro_brick_mapping0; + uint32_t emc_pmacro_brick_mapping1; + uint32_t emc_pmacro_brick_mapping2; + + uint32_t emc_pmacro_tx_sel_clk_src0; + uint32_t emc_pmacro_tx_sel_clk_src1; + uint32_t emc_pmacro_tx_sel_clk_src2; + uint32_t emc_pmacro_tx_sel_clk_src3; + uint32_t emc_pmacro_tx_sel_clk_src4; + uint32_t emc_pmacro_tx_sel_clk_src5; + + uint32_t emc_pmacro_ddll_bypass; + + uint32_t emc_pmacro_ddll_pwrd0; + uint32_t emc_pmacro_ddll_pwrd1; + uint32_t emc_pmacro_ddll_pwrd2; + + uint32_t emc_pmacro_cmd_ctrl0; + uint32_t emc_pmacro_cmd_ctrl1; + uint32_t emc_pmacro_cmd_ctrl2; /* DRAM size information */ /* Specifies the value for MC_EMEM_ADR_CFG */ - u_int32_t mc_emem_adr_cfg; + uint32_t mc_emem_adr_cfg; /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - u_int32_t mc_emem_adr_cfg_dev0; + uint32_t mc_emem_adr_cfg_dev0; /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - u_int32_t mc_emem_adr_cfg_dev1; + uint32_t mc_emem_adr_cfg_dev1; - u_int32_t mc_emem_adr_cfg_channel_mask; + uint32_t mc_emem_adr_cfg_channel_mask; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ - u_int32_t mc_emem_adr_cfg_bank_mask0; + uint32_t mc_emem_adr_cfg_bank_mask0; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - u_int32_t mc_emem_adr_cfg_bank_mask1; + uint32_t mc_emem_adr_cfg_bank_mask1; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - u_int32_t mc_emem_adr_cfg_bank_mask2; + uint32_t mc_emem_adr_cfg_bank_mask2; /* * Specifies the value for MC_EMEM_CFG which holds the external memory * size (in KBytes) */ - u_int32_t mc_emem_cfg; + uint32_t mc_emem_cfg; /* MC arbitration configuration */ /* Specifies the value for MC_EMEM_ARB_CFG */ - u_int32_t mc_emem_arb_cfg; + uint32_t mc_emem_arb_cfg; /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - u_int32_t mc_emem_arb_outstanding_req; + uint32_t mc_emem_arb_outstanding_req; - u_int32_t emc_emem_arb_refpb_hp_ctrl; - u_int32_t emc_emem_arb_refpb_bank_ctrl; + uint32_t emc_emem_arb_refpb_hp_ctrl; + uint32_t emc_emem_arb_refpb_bank_ctrl; /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - u_int32_t mc_emem_arb_timing_rcd; + uint32_t mc_emem_arb_timing_rcd; /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - u_int32_t mc_emem_arb_timing_rp; + uint32_t mc_emem_arb_timing_rp; /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - u_int32_t mc_emem_arb_timing_rc; + uint32_t mc_emem_arb_timing_rc; /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - u_int32_t mc_emem_arb_timing_ras; + uint32_t mc_emem_arb_timing_ras; /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - u_int32_t mc_emem_arb_timing_faw; + uint32_t mc_emem_arb_timing_faw; /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - u_int32_t mc_emem_arb_timing_rrd; + uint32_t mc_emem_arb_timing_rrd; /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - u_int32_t mc_emem_arb_timing_rap2pre; + uint32_t mc_emem_arb_timing_rap2pre; /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - u_int32_t mc_emem_arb_timing_wap2pre; + uint32_t mc_emem_arb_timing_wap2pre; /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - u_int32_t mc_emem_arb_timing_r2r; + uint32_t mc_emem_arb_timing_r2r; /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - u_int32_t mc_emem_arb_timing_w2w; + uint32_t mc_emem_arb_timing_w2w; /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - u_int32_t mc_emem_arb_timing_r2w; + uint32_t mc_emem_arb_timing_r2w; /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - u_int32_t mc_emem_arb_timing_w2r; + uint32_t mc_emem_arb_timing_w2r; - u_int32_t mc_emem_arb_timing_rfcpb; + uint32_t mc_emem_arb_timing_rfcpb; /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - u_int32_t mc_emem_arb_da_turns; + uint32_t mc_emem_arb_da_turns; /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - u_int32_t mc_emem_arb_da_covers; + uint32_t mc_emem_arb_da_covers; /* Specifies the value for MC_EMEM_ARB_MISC0 */ - u_int32_t mc_emem_arb_misc0; + uint32_t mc_emem_arb_misc0; /* Specifies the value for MC_EMEM_ARB_MISC1 */ - u_int32_t mc_emem_arb_misc1; - u_int32_t mc_emem_arb_misc2; + uint32_t mc_emem_arb_misc1; + uint32_t mc_emem_arb_misc2; /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - u_int32_t mc_emem_arb_ring1_throttle; + uint32_t mc_emem_arb_ring1_throttle; /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - u_int32_t mc_emem_arb_override; + uint32_t mc_emem_arb_override; /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - u_int32_t mc_emem_arb_override1; + uint32_t mc_emem_arb_override1; /* Specifies the value for MC_EMEM_ARB_RSV */ - u_int32_t mc_emem_arb_rsv; + uint32_t mc_emem_arb_rsv; - u_int32_t mc_da_cfg0; - u_int32_t mc_emem_arb_timing_ccdmw; + uint32_t mc_da_cfg0; + uint32_t mc_emem_arb_timing_ccdmw; /* Specifies the value for MC_CLKEN_OVERRIDE */ - u_int32_t mc_clken_override; + uint32_t mc_clken_override; /* Specifies the value for MC_STAT_CONTROL */ - u_int32_t mc_stat_control; + uint32_t mc_stat_control; /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - u_int32_t mc_video_protect_bom; + uint32_t mc_video_protect_bom; /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - u_int32_t mc_video_protect_bom_adr_hi; + uint32_t mc_video_protect_bom_adr_hi; /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - u_int32_t mc_video_protect_size_mb; + uint32_t mc_video_protect_size_mb; /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - u_int32_t mc_video_protect_vpr_override; + uint32_t mc_video_protect_vpr_override; /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - u_int32_t mc_video_protect_vpr_override1; + uint32_t mc_video_protect_vpr_override1; /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - u_int32_t mc_video_protect_gpu_override0; + uint32_t mc_video_protect_gpu_override0; /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - u_int32_t mc_video_protect_gpu_override1; + uint32_t mc_video_protect_gpu_override1; /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - u_int32_t mc_sec_carveout_bom; + uint32_t mc_sec_carveout_bom; /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - u_int32_t mc_sec_carveout_adr_hi; + uint32_t mc_sec_carveout_adr_hi; /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - u_int32_t mc_sec_carveout_size_mb; + uint32_t mc_sec_carveout_size_mb; /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ - u_int32_t mc_video_protect_write_access; + uint32_t mc_video_protect_write_access; /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ - u_int32_t mc_sec_carveout_protect_write_access; - - u_int32_t mc_generalized_carveout1_bom; - u_int32_t mc_generalized_carveout1_bom_hi; - u_int32_t mc_generalized_carveout1_size_128kb; - u_int32_t mc_generalized_carveout1_access0; - u_int32_t mc_generalized_carveout1_access1; - u_int32_t mc_generalized_carveout1_access2; - u_int32_t mc_generalized_carveout1_access3; - u_int32_t mc_generalized_carveout1_access4; - u_int32_t mc_generalized_carveout1_force_internal_access0; - u_int32_t mc_generalized_carveout1_force_internal_access1; - u_int32_t mc_generalized_carveout1_force_internal_access2; - u_int32_t mc_generalized_carveout1_force_internal_access3; - u_int32_t mc_generalized_carveout1_force_internal_access4; - u_int32_t mc_generalized_carveout1_cfg0; - - u_int32_t mc_generalized_carveout2_bom; - u_int32_t mc_generalized_carveout2_bom_hi; - u_int32_t mc_generalized_carveout2_size_128kb; - u_int32_t mc_generalized_carveout2_access0; - u_int32_t mc_generalized_carveout2_access1; - u_int32_t mc_generalized_carveout2_access2; - u_int32_t mc_generalized_carveout2_access3; - u_int32_t mc_generalized_carveout2_access4; - u_int32_t mc_generalized_carveout2_force_internal_access0; - u_int32_t mc_generalized_carveout2_force_internal_access1; - u_int32_t mc_generalized_carveout2_force_internal_access2; - u_int32_t mc_generalized_carveout2_force_internal_access3; - u_int32_t mc_generalized_carveout2_force_internal_access4; - u_int32_t mc_generalized_carveout2_cfg0; - - u_int32_t mc_generalized_carveout3_bom; - u_int32_t mc_generalized_carveout3_bom_hi; - u_int32_t mc_generalized_carveout3_size_128kb; - u_int32_t mc_generalized_carveout3_access0; - u_int32_t mc_generalized_carveout3_access1; - u_int32_t mc_generalized_carveout3_access2; - u_int32_t mc_generalized_carveout3_access3; - u_int32_t mc_generalized_carveout3_access4; - u_int32_t mc_generalized_carveout3_force_internal_access0; - u_int32_t mc_generalized_carveout3_force_internal_access1; - u_int32_t mc_generalized_carveout3_force_internal_access2; - u_int32_t mc_generalized_carveout3_force_internal_access3; - u_int32_t mc_generalized_carveout3_force_internal_access4; - u_int32_t mc_generalized_carveout3_cfg0; - - u_int32_t mc_generalized_carveout4_bom; - u_int32_t mc_generalized_carveout4_bom_hi; - u_int32_t mc_generalized_carveout4_size_128kb; - u_int32_t mc_generalized_carveout4_access0; - u_int32_t mc_generalized_carveout4_access1; - u_int32_t mc_generalized_carveout4_access2; - u_int32_t mc_generalized_carveout4_access3; - u_int32_t mc_generalized_carveout4_access4; - u_int32_t mc_generalized_carveout4_force_internal_access0; - u_int32_t mc_generalized_carveout4_force_internal_access1; - u_int32_t mc_generalized_carveout4_force_internal_access2; - u_int32_t mc_generalized_carveout4_force_internal_access3; - u_int32_t mc_generalized_carveout4_force_internal_access4; - u_int32_t mc_generalized_carveout4_cfg0; - - u_int32_t mc_generalized_carveout5_bom; - u_int32_t mc_generalized_carveout5_bom_hi; - u_int32_t mc_generalized_carveout5_size_128kb; - u_int32_t mc_generalized_carveout5_access0; - u_int32_t mc_generalized_carveout5_access1; - u_int32_t mc_generalized_carveout5_access2; - u_int32_t mc_generalized_carveout5_access3; - u_int32_t mc_generalized_carveout5_access4; - u_int32_t mc_generalized_carveout5_force_internal_access0; - u_int32_t mc_generalized_carveout5_force_internal_access1; - u_int32_t mc_generalized_carveout5_force_internal_access2; - u_int32_t mc_generalized_carveout5_force_internal_access3; - u_int32_t mc_generalized_carveout5_force_internal_access4; - u_int32_t mc_generalized_carveout5_cfg0; + uint32_t mc_sec_carveout_protect_write_access; + + uint32_t mc_generalized_carveout1_bom; + uint32_t mc_generalized_carveout1_bom_hi; + uint32_t mc_generalized_carveout1_size_128kb; + uint32_t mc_generalized_carveout1_access0; + uint32_t mc_generalized_carveout1_access1; + uint32_t mc_generalized_carveout1_access2; + uint32_t mc_generalized_carveout1_access3; + uint32_t mc_generalized_carveout1_access4; + uint32_t mc_generalized_carveout1_force_internal_access0; + uint32_t mc_generalized_carveout1_force_internal_access1; + uint32_t mc_generalized_carveout1_force_internal_access2; + uint32_t mc_generalized_carveout1_force_internal_access3; + uint32_t mc_generalized_carveout1_force_internal_access4; + uint32_t mc_generalized_carveout1_cfg0; + + uint32_t mc_generalized_carveout2_bom; + uint32_t mc_generalized_carveout2_bom_hi; + uint32_t mc_generalized_carveout2_size_128kb; + uint32_t mc_generalized_carveout2_access0; + uint32_t mc_generalized_carveout2_access1; + uint32_t mc_generalized_carveout2_access2; + uint32_t mc_generalized_carveout2_access3; + uint32_t mc_generalized_carveout2_access4; + uint32_t mc_generalized_carveout2_force_internal_access0; + uint32_t mc_generalized_carveout2_force_internal_access1; + uint32_t mc_generalized_carveout2_force_internal_access2; + uint32_t mc_generalized_carveout2_force_internal_access3; + uint32_t mc_generalized_carveout2_force_internal_access4; + uint32_t mc_generalized_carveout2_cfg0; + + uint32_t mc_generalized_carveout3_bom; + uint32_t mc_generalized_carveout3_bom_hi; + uint32_t mc_generalized_carveout3_size_128kb; + uint32_t mc_generalized_carveout3_access0; + uint32_t mc_generalized_carveout3_access1; + uint32_t mc_generalized_carveout3_access2; + uint32_t mc_generalized_carveout3_access3; + uint32_t mc_generalized_carveout3_access4; + uint32_t mc_generalized_carveout3_force_internal_access0; + uint32_t mc_generalized_carveout3_force_internal_access1; + uint32_t mc_generalized_carveout3_force_internal_access2; + uint32_t mc_generalized_carveout3_force_internal_access3; + uint32_t mc_generalized_carveout3_force_internal_access4; + uint32_t mc_generalized_carveout3_cfg0; + + uint32_t mc_generalized_carveout4_bom; + uint32_t mc_generalized_carveout4_bom_hi; + uint32_t mc_generalized_carveout4_size_128kb; + uint32_t mc_generalized_carveout4_access0; + uint32_t mc_generalized_carveout4_access1; + uint32_t mc_generalized_carveout4_access2; + uint32_t mc_generalized_carveout4_access3; + uint32_t mc_generalized_carveout4_access4; + uint32_t mc_generalized_carveout4_force_internal_access0; + uint32_t mc_generalized_carveout4_force_internal_access1; + uint32_t mc_generalized_carveout4_force_internal_access2; + uint32_t mc_generalized_carveout4_force_internal_access3; + uint32_t mc_generalized_carveout4_force_internal_access4; + uint32_t mc_generalized_carveout4_cfg0; + + uint32_t mc_generalized_carveout5_bom; + uint32_t mc_generalized_carveout5_bom_hi; + uint32_t mc_generalized_carveout5_size_128kb; + uint32_t mc_generalized_carveout5_access0; + uint32_t mc_generalized_carveout5_access1; + uint32_t mc_generalized_carveout5_access2; + uint32_t mc_generalized_carveout5_access3; + uint32_t mc_generalized_carveout5_access4; + uint32_t mc_generalized_carveout5_force_internal_access0; + uint32_t mc_generalized_carveout5_force_internal_access1; + uint32_t mc_generalized_carveout5_force_internal_access2; + uint32_t mc_generalized_carveout5_force_internal_access3; + uint32_t mc_generalized_carveout5_force_internal_access4; + uint32_t mc_generalized_carveout5_cfg0; /* Specifies enable for CA training */ - u_int32_t emc_ca_training_enable; + uint32_t emc_ca_training_enable; /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ - u_int32_t swizzle_rank_byte_encode; + uint32_t swizzle_rank_byte_encode; /* Specifies enable and offset for patched boot rom write */ - u_int32_t boot_rom_patch_control; + uint32_t boot_rom_patch_control; /* Specifies data for patched boot rom write */ - u_int32_t boot_rom_patch_data; + uint32_t boot_rom_patch_data; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - u_int32_t mc_mts_carveout_bom; + uint32_t mc_mts_carveout_bom; /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - u_int32_t mc_mts_carveout_adr_hi; + uint32_t mc_mts_carveout_adr_hi; /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - u_int32_t mc_mts_carveout_size_mb; + uint32_t mc_mts_carveout_size_mb; /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - u_int32_t mc_mts_carveout_reg_ctrl; + uint32_t mc_mts_carveout_reg_ctrl; /* End of generated code by warmboot_code_gen */ } nvboot_sdram_params; |