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* Remove "high 16" register class macros for xmm/ymm/zmmH. Peter Anvin2013-11-281-9/+3
* opflags: Separate vector registers into low-16 and high-16Jin Kyu Song2013-11-271-4/+23
* MPX: Add MPX instructionsJin Kyu Song2013-11-201-1/+4
* AVX-512: Add OPMASK instructionsJin Kyu Song2013-08-291-1/+3
* AVX-512: Add EVEX encoding and new instructionsJin Kyu Song2013-08-161-3/+3
* AVX-512: Add support for parsing bracesJin Kyu Song2013-08-061-6/+15
* BR 3392260: Handle instructions only separated by vector SIB sizeH. Peter Anvin2013-07-191-0/+2
* Drop SAME_AS flag from instruction matcherBen Rudiak-Gould2013-03-041-3/+0
* insns: Remove pushseg/popseg internal bytecodesBen Rudiak-Gould2013-03-031-4/+10
* Remove +sBen Rudiak-Gould2013-03-011-11/+6
* opflags: Rework opflags bits with OP_ macrosCyrill Gorcunov2012-09-161-163/+163
* opflags: Introduce opflags generating macrosCyrill Gorcunov2012-09-161-0/+4
* opflags: Drop never used REG_RIP/REG_EIPCyrill Gorcunov2012-09-161-3/+0
* opflags: Extend opflags_t to 64 bitsCyrill Gorcunov2012-09-101-84/+84
* Add IS_SREG and IS_FSGS helpersCyrill Gorcunov2011-08-281-0/+3
* Optimize mov r64,immH. Peter Anvin2010-08-241-7/+8
* opflags: more int32_t -> opflags_t conversionsH. Peter Anvin2009-10-131-0/+239