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* Accept implicit memory size for VMREAD/VMWRITEH. Peter Anvin2008-08-281-4/+4
* BR 2029472: Wrong operand size for VMREAD/VMWRITE in 64-bit modeH. Peter Anvin2008-08-281-2/+4
* BR 2028995: Missing MOVNTI m64, r64H. Peter Anvin2008-08-281-1/+2
* BR 2029829: Accept VIA XCRYPT instructions with or without REPH. Peter Anvin2008-08-281-8/+9
* BR 2039212: Handle indirect far jumps in 64-bit modeH. Peter Anvin2008-08-281-2/+6
* Add 256-bit AVX stores per the latest AVX spec.H. Peter Anvin2008-08-271-2/+7
* Add AVX forms of the AES instructions (new in the latest AVX spec)H. Peter Anvin2008-08-271-0/+12
* BR 2067820: add the MOVSXD instructionH. Peter Anvin2008-08-241-1/+2
* BR 2030823: Problem with the 256-bit FMA instructionsH. Peter Anvin2008-08-131-16/+16
* BR 2043111: Typo in insns.dat: VCMPFT_OQPD VCMPFT_OQPSH. Peter Anvin2008-08-131-2/+2
* BR 2025977: Handle SLDT with a 64-bit register operandH. Peter Anvin2008-07-301-0/+2
* BR 2023036: MOV reg32,dreg and vice versa are NOLONGH. Peter Anvin2008-07-201-2/+2
* BR 2017453: indirect jumps in 64-bit mode are implicitly 64 bitsH. Peter Anvin2008-07-131-4/+4
* Fix Bugs item #2017455 (LTR in long mode)Charles Crayne2008-07-131-2/+2
* AES instructions are WESTMERE, not NEHALEMH. Peter Anvin2008-06-271-7/+6
* The XSAVE group are SSE-spefix-sensitiveH. Peter Anvin2008-06-051-5/+6
* insns.dat: whitespace cleanupH. Peter Anvin2008-05-271-1/+1
* Fix double 66 prefixes on INVEPT/INVVPID (BR 1956955)H. Peter Anvin2008-05-271-2/+2
* VCVTPD2PS, VCVTPD2DQ, VCVTTPD2DQ mem need explicit op size (BR 1974170)H. Peter Anvin2008-05-261-6/+12
* Fix parameters to VCVTPD2DQ (BR 1974159)H. Peter Anvin2008-05-261-1/+1
* Fix mnemnonics for SSE5 PCOMU instructionsH. Peter Anvin2008-05-251-32/+32
* Fix mnemonics for VTESTP[SD] (BR 1971570)H. Peter Anvin2008-05-241-4/+4
* Fix the VPSHUF*W instructions (BR 1971567)H. Peter Anvin2008-05-241-2/+2
* Fix typo in VPCMPESTRM instruction (BR 1971565)H. Peter Anvin2008-05-241-1/+1
* Add VCVTSI2SS (BR 1971564)H. Peter Anvin2008-05-241-0/+4
* Fix immediate for PCLMULHQ* instructions (BR 1971555)H. Peter Anvin2008-05-241-2/+2
* Remove imm from specific versions of VCMPxxH. Peter Anvin2008-05-241-384/+384
* Add VLDQQU as an alias for 256-bit VLDDQU (BR 1971539)H. Peter Anvin2008-05-241-0/+1
* VFMSUBADDP[SD], not VFMADDSUBS[SD] (BR 1971573)H. Peter Anvin2008-05-241-4/+8
* AVX FMA: Instruction table for the AVX FMA instructionsH. Peter Anvin2008-05-231-0/+63
* AVX: Remaining AVX instructions (still need FMA)H. Peter Anvin2008-05-231-0/+73
* AVX instruction table through "P"H. Peter Anvin2008-05-231-0/+172
* AVX: instruction table up to PEH. Peter Anvin2008-05-211-8/+112
* AVX: instruction table through MH. Peter Anvin2008-05-211-8/+105
* Implement aliases for specific SSE5 compare operationsH. Peter Anvin2008-05-211-4/+144
* insns.dat: reimplement SSE5 compares using the bytecode compilerH. Peter Anvin2008-05-211-12/+12
* Add the PCLMUL instructions (BR 1933742)H. Peter Anvin2008-05-211-0/+8
* Add INVEPT and INVVPID (BR 1956955)H. Peter Anvin2008-05-211-0/+5
* Add the MOVBE instructions (BR 1956954)H. Peter Anvin2008-05-211-0/+9
* insns typo fix: SSE5 FNM* instructions misspelledH. Peter Anvin2008-05-211-32/+32
* Merge branch 'master' of git+ssh://repo.or.cz/srv/git/nasmH. Peter Anvin2008-05-211-0/+75
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| * AVX instructions up to VMINSSH. Peter Anvin2008-05-201-1/+33
| * A few more AVX instructions (up to VLDMXCSR)H. Peter Anvin2008-05-201-0/+43
* | UDx instructions are 186+, not 286+H. Peter Anvin2008-05-211-5/+5
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* Officially specify - as the symbol for an implicit operandH. Peter Anvin2008-05-201-4/+4
* AVX: implement all the convert instructions...H. Peter Anvin2008-05-201-0/+38
* Accept the gas mnemonics "ud2a" and "ud2b"; fix ud0H. Peter Anvin2008-05-201-1/+3
* Finish the VCMP series...H. Peter Anvin2008-05-201-0/+134
* More AVX instructionsH. Peter Anvin2008-05-201-22/+346
* PTEST is SSE4.1; although AMD says it's SSE5.H. Peter Anvin2008-05-201-1/+0
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