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* Unbreak CMPSW/CMPSD/CMPSQH. Peter Anvin2007-11-201-3/+3
* BR 1834292: Fix multiple disassembler bugsH. Peter Anvin2007-11-181-59/+59
* BR 993895: Support zero-operand floating-point insnH. Peter Anvin2007-11-151-3/+36
* Un-special-case "xchg rax,rax"; disassemble o64H. Peter Anvin2007-11-121-4/+5
* BR 1828866: fix handling of LAR/LSLH. Peter Anvin2007-11-121-0/+12
* Fix disassembly of XCHGH. Peter Anvin2007-11-121-1/+1
* Fix handling of XCHG in 64-bit modeH. Peter Anvin2007-11-121-5/+8
* More \321 -> \324 bug fixesH. Peter Anvin2007-11-121-17/+17
* 64-bit addressing and prefix handling changesH. Peter Anvin2007-10-281-3/+3
* Fix FISTTP opcodes (BR 689695)H. Peter Anvin2007-10-151-3/+3
* insns.dat: add systematic names for the hinting NOPs (0F18-0F1F)H. Peter Anvin2007-10-021-0/+194
* Correct the handling of "MOV" with immediate in 64-bit modeH. Peter Anvin2007-09-251-3/+3
* Fix BR 1490407: size of the second operand of LAR/LSLH. Peter Anvin2007-09-251-10/+10
* insns.dat: SMINT - mark ND, DMINT - fix opcodeH. Peter Anvin2007-09-241-2/+2
* Additional compaction missed by scriptH. Peter Anvin2007-09-241-6/+3
* insns.dat: machine-generated compaction mmx/xmmreg,mem -> mmx/xmmrmH. Peter Anvin2007-09-241-506/+253
* Implement INVLPGA according to the documentationH. Peter Anvin2007-09-221-0/+3
* Reformat insns.dat to uniform column widthH. Peter Anvin2007-09-221-1864/+1864
* Auto-generate 0x67 prefixes without the need for \30x codesH. Peter Anvin2007-09-221-896/+896
* LDDQU needs \301 (BR 1103549)H. Peter Anvin2007-09-221-1/+1
* RDTSCP and INVLPGA aren't 64-bit specificH. Peter Anvin2007-09-221-2/+2
* Cyrix GX1 instructions: BBx_RESET, CPU_READ, CPU_WRITEH. Peter Anvin2007-09-221-0/+4
* Centaur XSHA1, XSHA256, MONTMULH. Peter Anvin2007-09-221-0/+3
* Implement Centaur's XCRYPT instructionsH. Peter Anvin2007-09-221-7/+13
* Add Geode LX (AMD's Cyrix-derived core) instructionsH. Peter Anvin2007-09-221-0/+6
* Add the GETSEC instruction for Intel SMXH. Peter Anvin2007-09-221-0/+3
* Add the AMD SSE4a and LZCNT instructionsH. Peter Anvin2007-09-221-0/+13
* Tag UMOV as ND (no disassembly) to avoid collisionH. Peter Anvin2007-09-221-12/+12
* Merge commit 'origin/master' into sse5H. Peter Anvin2007-09-181-0/+3
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| * Add NOP with argument to the instruction listH. Peter Anvin2007-09-181-0/+3
* | Implement "oword" (128 bits) as a first-class sizeH. Peter Anvin2007-09-181-10/+16
* | SSE5 instruction tableH. Peter Anvin2007-09-181-0/+148
* | insns.dat: All SSE5 instructions are AMDH. Peter Anvin2007-09-171-16/+16
* | Actually generate SSE5 instructionsH. Peter Anvin2007-09-171-0/+18
* | Merge commit 'origin/master' into sse5H. Peter Anvin2007-09-171-1/+1
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| * CLFLUSH: Neither an x64 instruction nor AMDH. Peter Anvin2007-09-171-1/+1
* | Initial support for four arguments per instructionH. Peter Anvin2007-09-171-81/+81
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* Fix literal F2 and F3 prefixesH. Peter Anvin2007-09-121-64/+64
* Add (untested!) SSSE3, SSE4.1, SSE4.2 instructionsH. Peter Anvin2007-09-121-8/+80
* Add support for Tejas New Instructions (SSSE3)H. Peter Anvin2007-09-121-0/+33
* Remove $Id$ tags (useless with git)H. Peter Anvin2007-09-121-1/+0
* Use rm32 operands for VMREAD/VMWRITEH. Peter Anvin2007-09-121-4/+2
* Handle instructions which can have both REX.W and OSPH. Peter Anvin2007-09-111-2/+2
* Fix some MMX/SSE irregularities which interact with the 64-bit supportH. Peter Anvin2007-09-021-12/+12
* Fixed issues with REX prefix effective address generation. Fixed XMM instruct...Keith Kanios2007-08-171-227/+227
* Machine-generated \321->\324 correctionsH. Peter Anvin2007-05-301-148/+148
* More \321 -> \324H. Peter Anvin2007-05-301-2/+2
* MOV reg64,reg64 takes \324 (64 bit with REX) not \321 (32 bit)H. Peter Anvin2007-05-301-1/+1
* Handle "LOCK as REX.R" for MOV CRx; fix warning for invalid 64-bit regsH. Peter Anvin2007-04-171-2/+2
* MEM_OFFSET Instructions Fixed.Keith Kanios2007-04-161-4/+4
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