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* Add copyright notice to insns.datH. Peter Anvin2009-06-281-6/+35
* ndisasm: fix disassembly of JRCXZH. Peter Anvin2009-06-261-1/+1
* insns.dat: reformatH. Peter Anvin2009-06-261-104/+104
* insns.dat: add relaxed forms for XOP/FMA4/CVT16 instructionsH. Peter Anvin2009-06-261-146/+148
* insns: make the MMX version of PINSRW match the SSE/AVX onesH. Peter Anvin2009-06-241-3/+3
* Intel FMA: drop relaxed formsH. Peter Anvin2009-06-241-192/+192
* Fix the PINSR series of instructionsH. Peter Anvin2009-06-241-18/+21
* insns.dat: fix typos: VCMPORD_SP[SD] entered as VCMPORS_SP[SD]H. Peter Anvin2009-06-241-4/+2
* insns.dat: collapse relaxed formsH. Peter Anvin2009-06-241-1212/+608
* insns.dat - fixup for XOP (SSE5) AMD instructionsCyrill Gorcunov2009-05-171-13/+23
* insns.dat - introcuce base XOP (SSE5) AMD instructionsCyrill Gorcunov2009-05-151-0/+199
* BR 2690688: Fix opcodes for FMA instructionsH. Peter Anvin2009-03-171-264/+264
* BR 2690688: add missing VFM instructionsH. Peter Anvin2009-03-171-24/+168
* BR 2689316: PEXTRQ requires REX.WH. Peter Anvin2009-03-161-1/+1
* insns.dat: fix VFNM instructions incorrectly spelled as VFMNH. Peter Anvin2009-03-161-48/+48
* Add VPCLMUL instructionsH. Peter Anvin2009-02-231-0/+12
* PCLMUL is apparently targeted for Westmere with the AES stuffH. Peter Anvin2009-02-211-6/+5
* BR 2557903: fix disassembly of a set of SSE MOV* instructionsH. Peter Anvin2009-02-211-6/+6
* BR 2541252: Fix issues in insns.dat, mostly related to LZCNT and POPCNTH. Peter Anvin2009-02-211-10/+10
* BR 2592476: Treat WAIT as a prefix even though it's really an instructionH. Peter Anvin2009-02-211-11/+10
* Fix opcode for VADDSUBPS; operands for VBLEND; add SSE for AES opsH. Peter Anvin2009-02-211-14/+14
* FMA instructions won't be in Sandy BridgeH. Peter Anvin2009-02-211-241/+240
* Update the VFMA* instructions per the AVX spec version 5H. Peter Anvin2009-02-181-64/+240
* insns.dat: fix minor formatting anomaliesH. Peter Anvin2009-02-181-3/+3
* BR 2413278: Nonoptimal forms of arithmetic instructions involving AXH. Peter Anvin2008-12-291-0/+24
* The POPCNT instruction does not need sizes on memory operandsH. Peter Anvin2008-11-061-3/+3
* BR 2229703: POPCNT r64,rm64 not POPCNT r64,rm32H. Peter Anvin2008-11-061-1/+1
* The CRC32 instructions can take 66 prefixes as well as F2H. Peter Anvin2008-10-231-5/+5
* BR 2190521: fix the CRC32 opcodesH. Peter Anvin2008-10-231-5/+5
* BR 2187210: Fix PFRCPV and PFRSQRTVH. Peter Anvin2008-10-221-2/+2
* Reshuffle and move the bytecodes for segment register push/popH. Peter Anvin2008-10-081-5/+5
* Add missing IMUL pattern: reg64,imm8H. Peter Anvin2008-10-071-0/+1
* Add a few missing \15 -> \275 conversionsH. Peter Anvin2008-10-071-6/+6
* Change \40 class opcodes to \254, except IMULH. Peter Anvin2008-10-071-12/+12
* New opcode for 32->64 bit sign-extended immediate with warningH. Peter Anvin2008-10-071-1/+1
* New opcodes to deal with 8-bit immediate sign extended to opsizeH. Peter Anvin2008-10-061-19/+19
* Better warnings for out-of-range valuesH. Peter Anvin2008-10-061-24/+0
* BR 2148476: Fix arguments for a bunch of the CVT* instructionsH. Peter Anvin2008-10-061-22/+34
* JMP reg64 does not require a REX.W prefix.H. Peter Anvin2008-09-251-1/+1
* Accept implicit memory size for VMREAD/VMWRITEH. Peter Anvin2008-08-281-4/+4
* BR 2029472: Wrong operand size for VMREAD/VMWRITE in 64-bit modeH. Peter Anvin2008-08-281-2/+4
* BR 2028995: Missing MOVNTI m64, r64H. Peter Anvin2008-08-281-1/+2
* BR 2029829: Accept VIA XCRYPT instructions with or without REPH. Peter Anvin2008-08-281-8/+9
* BR 2039212: Handle indirect far jumps in 64-bit modeH. Peter Anvin2008-08-281-2/+6
* Add 256-bit AVX stores per the latest AVX spec.H. Peter Anvin2008-08-271-2/+7
* Add AVX forms of the AES instructions (new in the latest AVX spec)H. Peter Anvin2008-08-271-0/+12
* BR 2067820: add the MOVSXD instructionH. Peter Anvin2008-08-241-1/+2
* BR 2030823: Problem with the 256-bit FMA instructionsH. Peter Anvin2008-08-131-16/+16
* BR 2043111: Typo in insns.dat: VCMPFT_OQPD VCMPFT_OQPSH. Peter Anvin2008-08-131-2/+2
* BR 2025977: Handle SLDT with a 64-bit register operandH. Peter Anvin2008-07-301-0/+2
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