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authorH. Peter Anvin <hpa@zytor.com>2009-02-21 18:22:56 -0800
committerH. Peter Anvin <hpa@zytor.com>2009-02-21 18:22:56 -0800
commitc2acf7b047492a6d1cbc4ac3aeafc3812fdcc46b (patch)
treeb1459da6cf2de42b60b68f3b68f6192fd1840921 /assemble.c
parentf8ad53216f09f731cc9440fd599b64eb9ce433d8 (diff)
downloadnasm-c2acf7b047492a6d1cbc4ac3aeafc3812fdcc46b.tar.gz
BR 2592476: Treat WAIT as a prefix even though it's really an instruction
WAIT is technically an instruction, but from an assembler standpoint it behaves as if it had been a prefix. In particular, it has to be ordered *before* any real hardware prefixes.
Diffstat (limited to 'assemble.c')
-rw-r--r--assemble.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/assemble.c b/assemble.c
index 2668857a..ad7ea706 100644
--- a/assemble.c
+++ b/assemble.c
@@ -100,6 +100,7 @@
* \336-\337 are still listed as prefixes in the disassembler.
* \340 - reserve <operand 0> bytes of uninitialized storage.
* Operand 0 had better be a segmentless constant.
+ * \341 - this instruction needs a WAIT "prefix"
* \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
* (POP is never used for CS) depending on operand 0
* \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
@@ -464,6 +465,9 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
for (j = 0; j < MAXPREFIX; j++) {
uint8_t c = 0;
switch (instruction->prefixes[j]) {
+ case P_WAIT:
+ c = 0x9B;
+ break;
case P_LOCK:
c = 0xF0;
break;
@@ -1023,6 +1027,11 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
length += ins->oprs[0].offset;
break;
+ case 0341:
+ if (!ins->prefixes[PPS_WAIT])
+ ins->prefixes[PPS_WAIT] = P_WAIT;
+ break;
+
case4(0344):
length++;
break;
@@ -1674,6 +1683,9 @@ static void gencode(int32_t segment, int64_t offset, int bits,
}
break;
+ case 0341:
+ break;
+
case 0344:
case 0345:
bytes[0] = c & 1;