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* anv: Memset array propertiesJason Ekstrand2020-01-141-0/+5
| | | | | | | | | | | | This is probably better than possibly leaving those bytes uninitialized even if the app will theoretically not use them. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369> (cherry picked from commit 7978f2401bba7e60f255337a394fd132082be9aa)
* anv: Don't over-advertise descriptor indexing featuresJason Ekstrand2020-01-141-15/+17
| | | | | | | | | | We should only advertise sub-features if we advertise the extension. Fixes: 6e230d7607f "anv: Implement VK_EXT_descriptor_indexing" Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369> (cherry picked from commit d36eed3e695d8f39495a3d81373a8c47853bae7e)
* intel/blorp: Fill out all the dwords of MI_ATOMICJason Ekstrand2020-01-141-0/+4
| | | | | | | | | | This makes us valgrind clean again. Fixes: 9175c7058efb "intel/blorp: Make blorp update the clear color..." Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366> (cherry picked from commit d7ff137445b9bfd0cf15d176d0d152d16634559f)
* intel/vec4: Support scoped_memory_barrierJason Ekstrand2020-01-141-1/+2
| | | | | | | Fixes: 06aecb14c0476 "anv: Implement VK_KHR_vulkan_memory_model" Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307> (cherry picked from commit ada49bae5e039b10913bc61ba7b037227e7e49aa)
* aco: disable add combining for ds_swizzle_b32Rhys Perry2020-01-141-1/+1
| | | | | | | | | | ds_bpermute_b32/ds_permute_b32 are fine, I think Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler') Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081> (cherry picked from commit ef8abfa7908974f571786e83b047b187af0e48c7)
* aco: set exec_potentially_empty for demotesRhys Perry2020-01-141-0/+6
| | | | | | | | Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler') Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081> (cherry picked from commit 8f291dc14600c614788301e3265ff7f0f48b8b0d)
* aco: fix uninitialized data in the binaryRhys Perry2020-01-141-1/+5
| | | | | | | | Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-By: Timur Kristóf <timur.kristof@gmail.com> Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler') Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081> (cherry picked from commit bbac52873f4248c2f545f12137bd24071a8043cc)
* aco: fix imageSize()/textureSize() with large buffers on GFX8Rhys Perry2020-01-141-19/+15
| | | | | | | | | | | | | Tested on Navi by using dEQP-VK.image.image_size.buffer.* and the GFX8 path with the size multipled by the stride. dEQP-VK.image.image_size.buffer.* was also run with the tests modified to use a 96bit format. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler') Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081> (cherry picked from commit fcd6d8324560b5897586cbf8161f9b46bff5d11f)
* aco: set vm for pos0 exports on GFX10Rhys Perry2020-01-142-3/+6
| | | | | | | | | | RADV's LLVM backend and radeonsi does the same thing. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Cc: 19.3 <mesa-stable@lists.freedesktop.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081> (cherry picked from commit 49bcd06f974dcd8f60b4aa7d93bf1843439126a2)
* intel/fs/gen8+: Fix r127 dst/src overlap RA workaround for EOT message payload.Francisco Jerez2020-01-141-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | The problem occured when the return payload of a SIMD8 SEND instruction was re-used as source payload of an EOT SEND message. In such cases the interference edge added by that workaround between the payload and grf127_send_hack_node would have no effect, because the payload would be allocated to a fixed range of registers containing r127 by the special handling of EOT message payloads in the same function. This would cause things to blow up if the source payload of the first SIMD8 message ended up being allocated to a range which happened to overlap the destination. Fix it by avoiding r127 altogether in the allocation of EOT message payloads. The problem can be reproduced on ICL with the fp-indirections2 Piglit test-case in combination with the other optimizer changes of this series. Fixes: 232ed8980217 "i965/fs: Register allocator shoudn't use grf127 for sends dest" Cc: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 0703eab0120f20451e75ba8d4ce065350ad36fef)
* intel/fs/gen11+: Handle ROR/ROL in lower_simd_width().Francisco Jerez2020-01-141-0/+2
| | | | | | | | | | | | | | | | | | | Prevents invalid code from being emitted for ROR/ROL instructions in SIMD32 shaders. The problem can be reproduced with the following tests while forcing SIMD32 to be used for fragment shaders: piglit.shaders.glsl-rotate-left piglit.shaders.glsl-rotate-right However the issue could occur in production already with compute shaders and a workgroup size large enough to trigger SIMD32 dispatch. Fixes: 83fdec0f0de "intel/compiler: Enable the emission of ROR/ROL instructions" Cc: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 0a6e46d44d30fd10ee6784c9a6920b4d127e9810)
* glsl: Fix software 64-bit integer to 32-bit float conversions.Francisco Jerez2020-01-141-22/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation was broken for any integers between 2^24 and 2^30 (it would return zero for me on ICL). The reason is that for such integers we wouldn't take the 'if (0 <= shiftCount)' early return path, however 'shiftCount + 7' would be positive, leading to a negative 'count' argument passed to __shift64RightJamming(), which would give undefined results. This reworks the affected conversion functions to use either __shortShift64Left() or __shift64RightJamming() based on the sign of the final shift count, which should avoid the problem. In addition this should qualify as a clean-up/optimization -- This implementation of the conversion functions translates to 7 instructions less than the original on Intel hardware. This fixes the 'KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot' conformance tests on soft fp64 hardware with large enough subgroup size (>16). Fixes: d5cf6e92b4f7 "glsl: Add built-in functions to do uint64_to_fp32(uint64_t)" Fixes: c9d333a6b76e "glsl: Add built-in functions to do int64_to_fp32(int64_t)" Cc: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> (cherry picked from commit a30bb25a7a495db7b7cb3be50431029f48019fc3)
* mesa/st: fix a memory leak in get_versionAndrii Simiklit2020-01-141-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | This patch prevents memory leak in get_version function in st_manager.c This issue was found by valgrind: 16 bytes in 1 blocks are definitely lost in loss record 6 of 1,418 at 0x483CD99: calloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so) by 0x63D9476: st_init_extensions (st_extensions.c:1679) by 0x63B803B: get_version (st_manager.c:1271) by 0x63B8124: st_api_query_versions (st_manager.c:1289) by 0x63266EF: dri_init_screen_helper (dri_screen.c:583) by 0x6321B12: dri2_init_screen (dri2.c:2110) by 0x631AACC: driCreateNewScreen2 (dri_util.c:155) by 0x5D58192: dri3_create_screen (dri3_glx.c:897) by 0x5D39829: AllocAndFetchScreenConfigs (glxext.c:815) by 0x5D39C57: __glXInitialize (glxext.c:941) by 0x5D3290A: GetGLXPrivScreenConfig (glxcmds.c:174) by 0x5D34F38: glXQueryExtensionsString (glxcmds.c:1307) Fixes: eca8032f20d0970184843d98e2bddb688e94a3a9 ("gallium: Add ARB_gl_spirv support") Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3345> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3345> (cherry picked from commit ebaab89761aad59c4debec67c3ec24a96cb82dd1)
* freedreno/drm: Fix memory leak in softpin implementationLasse Lopperi2020-01-141-0/+2
| | | | | | | | | | | | | | | | | Free the memory allocated for cmds/reloc_bos array when destoying the associated ringbuffer. For similar fix for the non-softpin implementation see: https://gitlab.freedesktop.org/mesa/mesa/commit/d014af98b7afc69f4f733c8b8b6f2e3438e68407 Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2324 Fixes: f3cc0d2 ("freedreno: import libdrm_freedreno + redesign submit") Signed-off-by: Lasse Lopperi <lasse.lopperi@ge.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3342> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3342> (cherry picked from commit 3de2774dcb85fb2f87ae65a854fc5f25f0f34a91)
* radeonsi: release saved resources in si_compute_do_clear_or_copyPierre-Eric Pelloux-Prayer2020-01-141-0/+2
| | | | | | Fixes: 9b331e462e5 ("radeonsi: use compute shaders for clear_buffer & copy_buffer") Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit a5fe84aefb6858bee123f60b330db1e0287f9cc0)
* radeonsi: release saved resources in si_compute_copy_imagePierre-Eric Pelloux-Prayer2020-01-141-0/+3
| | | | | | Fixes: 1b25d340b79 ("radeonsi: use compute for resource_copy_region when possible") Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 1acf714d579114ff591c00989b2e6a97de8830b8)
* radeonsi: release saved resources in si_compute_clear_render_targetPierre-Eric Pelloux-Prayer2020-01-141-0/+2
| | | | | | Fixes: 984fd735152 ("radeonsi: use compute for clear_render_target when possible") Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit e1e87466ae7d46c564fdd3154003ae3cddf3147b)
* radeonsi: release saved resources in si_compute_expand_fmaskPierre-Eric Pelloux-Prayer2020-01-141-0/+1
| | | | | | Fixes: 095a58204d9 ("radeonsi: expand FMASK before MSAA image stores are used") Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 6c019e28caf2124b13d2ea5d87e936bf43d8b4fd)
* radeonsi: release saved resources in si_retile_dccPierre-Eric Pelloux-Prayer2020-01-141-0/+4
| | | | | | | Fixes: 1f21396431a ("radeonsi: add support for displayable DCC for multi-RB chips") Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2330 Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 9211cbe07a0ffb0abdaf3da68f7aa3ee00a430d7)
* anv: Flag descriptors dirty when gl_NumWorkgroups is usedJason Ekstrand2020-01-141-1/+8
| | | | | | Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> (cherry picked from commit ae72d1238c758404df045a82c36803dbccd93b31)
* anv: fix intel perf queries availability writesLionel Landwerlin2020-01-141-14/+5
| | | | | | | | | | The availability is not written at the location changed in ee6fbb95a74d... Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: ee6fbb95a74d ("anv: Properly handle host query reset of performance queries") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 60e0db3bfb05660fb3d2c868838635d667f8966a)
* mesa: Prevent _MaxLevel from being less than zeroThong Thai2020-01-091-1/+1
| | | | | | | | | | | When decoding using VDPAU, the _MaxLevel value becomes -1 due to NumLevels being equal to 0 at a certain point, and decoding fails due to an assertion later on. Signed-off-by: Thong Thai <thong.thai@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 3a4f8c8158df304af08681edbbfdfd40e43a6829)
* ac/gpu_info: always use distributed tessellation on gfx10Marek Olšák2020-01-091-2/+2
| | | | | | | | This might fix a hang on Navi14. Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (cherry picked from commit 186335d17d69c4a6b0ad69b82fe0744e4910645e)
* anv: don't close invalid syncfd semaphoreLionel Landwerlin2020-01-081-1/+2
| | | | | | | | Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 4578d4ae524ad433933e077bce6a0b85643e3f25)
* radeonsi: check ctx->sdma_cs before using itPierre-Eric Pelloux-Prayer2020-01-081-1/+2
| | | | | | | | | | | | | | | e5167a9276de1f383888714b41d3a9be2b9c1da9 disabled SDMA for gfx8. This caused 3 piglit arb_sparse_buffer tests (basic, buffer-data and commit) to crash on GFX8. Reported-by: Michel Dänzer <michel@daenzer.net> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Fixes: e5167a9276d ("radeonsi: disable SDMA on gfx8 to fix corruption on RX 580") (cherry picked from commit 5f8daae4d829c9f734d2f41058990809d2dba349) Conflicts resolved by Dylan Baker Conflicts: src/gallium/drivers/radeonsi/si_buffer.c
* main: allow external textures for BindImageTextureYevhenii Kolesnikov2020-01-081-1/+5
| | | | | | | | | | | | | | From issue 10 of the OES_EGL_image_external_essl3: A limited set of use-cases is enabled by making glBindImageTexture accept external textures. Shaders can access such external textures using the existing <image2D> sampler type. Fixes: 02a6d901eee ("mesa: add OES_EGL_image_external_essl3 support") Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit ed43dd62acc045e71d73dc28b74b6a9a9d52286f)
* intel/nir: Add a memory barrier before barrier()Jason Ekstrand2020-01-081-0/+14
| | | | | | | | | | | | Our barrier instruction does not implicitly do a memory fence but the GLSL barrier() intrinsic is supposed to. The easiest back-portable solution is to just add the NIR barriers. We'll sort this out more properly in later commits. Cc: mesa-stable@lists.freedesktop.org Closes: #2138 Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> (cherry picked from commit 803fad43c3f9a89f0d8409bd33280b5457b104c7)
* radv: Emit a BATCH_BREAK when changing pixel shaders or CB_TARGET_MASK.Bas Nieuwenhuizen2020-01-083-18/+65
| | | | | | | | | | | | | | | | | | | | | | | Fixes a hang on Raven with Resident Evil 2. I did not find anything more restricted to fix it: - Setting persistent_states_per_bin to 1 fixes it too, but likely does an internal break on any descriptor set changes too. - Only breaking the batch when cb_target_mask changes does not fix it (and looking at AMDVLK comments, I suspect the code in radeonsi should really be doing a FLUSH_DFSM). - Always doing a FLUSH_DFSM on shader switch helps, but that is more often than this and I don't think we should be doing that when DFSM is disabled. - Also emitting the existing break on framebuffer change when DFSM is disabled does not fix the issue. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2315 CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 7cc0702bbb955010600fcb2685edb4ba703561a8)
* radeonsi: disable SDMA on gfx8 to fix corruption on RX 580Marek Olšák2020-01-071-0/+5
| | | | | | | | | | | | | Closes: #1399 Closes: #1889 Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-By: Timur Kristóf <timur.kristof@gmail.com> (cherry picked from commit e5167a9276de1f383888714b41d3a9be2b9c1da9) Conflicts: src/gallium/drivers/radeonsi/si_pipe.c
* glsl/nir: do not change an element index to have correct block nameAndrii Simiklit2020-01-071-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | When SSBO array is used with packed layout, both IR tree and as a result, NIR tree will be incorrect. In fact, the SSBO dereference indices won't match the array size in some cases like the following: "layout(packed, binding=1) buffer SSBO { vec4 a; } ssbo[3]; out vec4 color; void main() { color = ssbo[2].a; }" After linking the IR and then NIR will have an SSBO array definition with size 1 but dereference still will have index 2 and linked_shader->Program->sh.ShaderStorageBlocks will contain just SSBO with name "SSBO[2]" So this line should be removed at least as a workaround for now to avoid error like: Failed to find the block by name "SSBO[0]" Fixes: 810dde2a "glsl/nir: Add a pass to lower UBO and SSBO access" Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit be6d51e1e3a2b2165cd21fbdda2527d10f4ce9ff)
* glsl: fix a binding points assignment for ssbo/ubo arraysAndrii Simiklit2020-01-073-13/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed to be in agreement with spec requirements: https://github.com/KhronosGroup/OpenGL-API/issues/46 Piers Daniell: "We discussed this in the OpenGL/ES working group meeting and agreed that eliminating unused elements from the interface block array is not desirable. There is no statement in the spec that this takes place and it would be highly implementation dependent if it happens. If the application has an "interface" in the shader they need to match up with the API it would be quite confusing to have the binding point get compacted. So the answer is no, the binding points aren't affected by unused elements in the interface block array." v2: - 'original_dim_size' field moved above to keep the struct packed better on 64-bit - added a comment for 'total_num_array_elements' field - fixed a binding point calculations for SSBOs array of arrays ( Ian Romanick <ian.d.romanick@intel.com> ) - fixed binding point calculations for non-packed SSBOs v3: - rename 'total_num_array_elements' to 'aoa_size' ( Jason Ekstrand <jason@jlekstrand.net> ) - rename 'boffset' to 'binding_stride' ( Alejandro Piñeiro <apinheiro@igalia.com> ) Fixes: 8cf1333b "glsl: link uniform block arrays of arrays" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532 Reported-By: Ilia Mirkin <imirkin@alum.mit.edu> Tested-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit 4beb0a23088e68693e94599ef36eb41cbcd59289)
* glsl: fix an incorrect max_array_access after optimization of ssbo/uboAndrii Simiklit2020-01-071-0/+1
| | | | | | | | | | | | | | This is needed to fix these tests: piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_frag piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_comp Fixes: 8cf1333b "glsl: link uniform block arrays of arrays" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532 Reported-By: Ilia Mirkin <imirkin@alum.mit.edu> Tested-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit a3c9a2881e242b9ac588d6dcb158e805fefe352d)
* radv: Only use the gfx mipmap level offset/pitch for linear textures.Bas Nieuwenhuizen2020-01-071-2/+6
| | | | | | | | | | | | | | | | | The tiled-case is non-sensical for non-base mips, but Vulkan requires that this function handles it but at the same time does not require returning anything useful. So we can basically return anything. Correct tiled pitch and offset are still required for our own WSI and in the future getting the layouts of images with DRM format modifiers. Both don't have to deal with images with more than 1 level though. Fixes: 824bd0830e8 "radv: return the correct pitch for linear mipmaps on GFX10" Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2301 Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2304 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 17741a0a05722245314e8ce9a3d5191feb63d9bd)
* radv: return the correct pitch for linear mipmaps on GFX10Samuel Pitoiset2020-01-073-2/+6
| | | | | | | | | | | | | On GFX9, the pitch of a level is always the pitch of the entire image but not on GFX10. This fixes graphics glithes with Halo - The Master Chief Collection. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2188 CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 824bd0830e811a7b6347bbd5c30e0a76bc7daf60)
* spirv: Fix glsl type assert in spir2nir.Bas Nieuwenhuizen2020-01-071-0/+4
| | | | | | | | | | Fixes: 624789e3708 "compiler/glsl: handle case where we have multiple users for types" Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 96c9483ccf5bc9116f7b754a0ccbc09097275083) Conflicts: src/compiler/spirv/spirv2nir.c
* r600: Fix maximum line widthGert Wollny2020-01-071-4/+1
| | | | | | | | | | | | | | | | | | | | There are only 13 bits available to store the line width, hence it can't be larger than 8191 v2: Add Fixes tag v3: - Unify value since for all r600 archs (Konstantin Kharlamov) - Correct the value the line width value is emitted as a 12.4 fixed point value of 1/2 line width on r600-r700 and as 8 * line width on Evergreen and newer. Fixes: 06bfb2d28f7adca7edc6be9c210a7a3583023652 r600: fork and import gallium/radeon Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286> (cherry picked from commit e8559ae4484c3240c81c0cbf49caf5be338f8395)
* anv: Ignore some CreateInfo structs when rasterization is disabledCaio Marcelo de Oliveira Filho2020-01-072-18/+38
| | | | | | | | | | | | | | | | | | | | | According to the description of VkGraphicsPipelineCreateInfo(), pViewportState, pMultisampleState, pDepthStencilState and pColorBlendState must be ignored when rasterization is not enabled. This avoids potentially invalid pointers being dereferenced when rasterization is disabled. Tested with `demos_x64 VK_Parameter_Zoo` from Renderdoc repository. v2: Don't store the `raster_enabled` as part of anv_pipeline, just query it from the create info. This avoids storing a state that's only used during pipeline creation. (Jason) Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2258 Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Eric Engestrom <eric@engestrom.ch> [v1] Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> [v1] Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 75a19186b2aad7e588f04e1c554cdfd315dd848a)
* nir: Add clone/hash/serialize support for non-uniform tex instructions.Bas Nieuwenhuizen2020-01-073-1/+12
| | | | | | | | | | | | | | These were missed when the fields got added. Added it everywhere where texture_index got used and it made sense. Found this in "The Surge 2", where the inliner does not copy the fields, resulting in corruption and hangs. Fixes: 3bd54576415 "nir: Add a lowering pass for non-uniform resource access" Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1203 Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3246> (cherry picked from commit 69bdc1c5fccbd9c0ef5354675b069ffb1383769e)
* aco: Fix uniform i2i64.Timur Kristóf2020-01-071-1/+1
| | | | | | | | | | | | | Fixes 240 failing test cases in dEQP-VK.spirv_assembly which were failing due to a bad s_ashr_i32 instruction. This commit fixes the instruction format along with the definitions of the instruction. Fixes: 11f43caaeca166c96ae49dbd506b6f58dd4a13fb Cc: 19.3 <mesa-stable@lists.freedesktop.org> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (cherry picked from commit 11e62a9734c631fa38f1e7b415f5b98f6a28589f)
* winsys/radeon: initialize pte_fragment_sizeMarek Olšák2020-01-071-0/+1
| | | | | | | | | Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org> Closes: #2179 Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 84b82f8cd1c9d0a03e68af3a68fb0b009be70780)
* meta: Cleanup function for DrawTexYevhenii Kolesnikov2020-01-071-0/+14
| | | | | | | | | | | | | Buffer object was never freed, causing memory leaks. Fixes: 76cfe2bc443 ("meta: Don't pollute the buffer object namespace in _mesa_meta_DrawTex") CC: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1390> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1390> (cherry picked from commit b318bc2072d42a58b491dac3aa6118012d92e5bb)
* amd/common: Handle alignment of 96-bit formats.Bas Nieuwenhuizen2020-01-071-0/+11
| | | | | | | | | | addrlib doesn't quite do it right, so do it ourselves. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2162 CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 88f567b5ce3c692dbee60ba58df3af7c614e4333)
* mesa: avoid returning a value in a void functionEric Engestrom2020-01-071-1/+2
| | | | | | | | Fixes: 1d1722e91070d7c37687 ("mesa: add EXT_dsa NamedProgram functions") Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit a6873a8df2393777975ae3043a395d79e495b365)
* nine: fix empty-body-issuesEric Engestrom2020-01-071-1/+1
| | | | | | | Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Fixes: 8d43e2b2ded0fe3c82d4 ("meson: add -Werror=empty-body to disallow `if(x);`") Reviewed-By: Timur Kristóf <timur.kristof@gmail.com> (cherry picked from commit ff3a2576a45e012b1cd8fbf73b9967083d6fce0e)
* amd: fix empty-body issuesEric Engestrom2020-01-074-9/+9
| | | | | | | Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Fixes: 8d43e2b2ded0fe3c82d4 ("meson: add -Werror=empty-body to disallow `if(x);`") Reviewed-By: Timur Kristóf <timur.kristof@gmail.com> (cherry picked from commit 51569e525afc5e7173f12b0a3f1ba0e92425407f)
* util/format: remove left-over util_format_description_table declarationEric Engestrom2020-01-071-4/+0
| | | | | | | Fixes: 3c45c4bc44310c1af4f0 ("util: Cope with the fact that formats in u_format.csv are not ordered.") Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit cc7a64f101be0939c17231257701230859dee90d)
* radv: Expose all sample counts for integer formats as well.Bas Nieuwenhuizen2020-01-071-1/+1
| | | | | | | | | Things work the same between float and integer. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2261 CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit a435f002c40f5adc99d37e65cf6b8bd478dc8e71)
* anv: Properly advertise sampledImageIntegerSampleCountsJason Ekstrand2020-01-071-1/+1
| | | | | | | | | | We support the same set of samples for integer color formats as for non-integer. We've been advertising it wrong since before the initial Vulkan 1.0 release. :-( Fixes: d68974530371 "vk/0.210.0: Rework device features and limits" Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit ac70442ce1f061a42649f7c88c6a8d278fb73fb5)
* radeon/vcn2: enable rate control for hevc encodingPierre-Eric Pelloux-Prayer2020-01-071-1/+7
| | | | | | | | | | | Based on b0626c1f306 ("radeon/vcn: enable rate control for hevc encoding"). Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2225 Fixes: 587b9c5dae6 ("radeon/vcn: implement vcn 2.0 encode") Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134> (cherry picked from commit 9c2a3b4e7566108ad336c253e3cd0fcb2629ae6d)
* etnaviv: update resource status after flushingChristian Gmeiner2020-01-071-0/+8
| | | | | | | | | | | | Currently piglit spec@arb_occlusion_query@occlusion_query_conform spins for ever as the resource status is never reset. See etna_hw_get_query_result(..) for more details. Fixes: 1456aa61cc5 ("etnaviv: Rework resource status tracking") CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: Marek Vasut <marex@denx.de> (cherry picked from commit 6e75f2172b5cc9298dee6f17e55bed60ce0c15fb)
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