summaryrefslogtreecommitdiff
path: root/src/gallium/drivers/virgl
Commit message (Expand)AuthorAgeFilesLines
* virgl: Increase the shader transfer buffer by doubling the sizeGert Wollny2019-12-171-2/+3
* virgl: Remove formats with unusual sample count.Lepton Wu2019-10-241-0/+3
* gallium: remove PIPE_SHADER_CAP_SCALAR_ISAMarek Olšák2019-10-101-2/+0
* gallium: add PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE to skip util_range lockMarek Olšák2019-10-076-9/+9
* virgl: modify internal structures to track winsys-supplied dataGurchetan Singh2019-10-022-43/+52
* virgl: modify resource_create_from_handle(..) callbackGurchetan Singh2019-10-022-2/+13
* virgl: Fix pipe_resource leaks under multi-sample.Lepton Wu2019-09-101-1/+3
* virgl: fix format conversion for recent gallium changes.Dave Airlie2019-08-266-16/+303
* virgl: check scanout maskGurchetan Singh2019-08-082-0/+7
* virgl: fixup_readback_format --> fixup_formatsGurchetan Singh2019-08-081-8/+7
* virgl: access caps in a less verbose way in virgl_is_format_supportedGurchetan Singh2019-08-081-9/+9
* virgl: Enable depth_clamp by lowering if the host is new enough.Gert Wollny2019-08-012-1/+8
* virgl: make use of local variableEric Engestrom2019-07-311-1/+1
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-1/+1
* gallium: switch boolean -> bool at the interface definitionsIlia Mirkin2019-07-225-51/+51
* virgl: fix a sync issue in virgl_buffer_transfer_extendChia-I Wu2019-07-191-62/+15
* virgl: rework virgl_transfer_queue_extendChia-I Wu2019-07-193-25/+24
* virgl: fix virgl_buffer_transfer_extendChia-I Wu2019-07-191-0/+1
* virgl: Set meta data for textures from handle.Lepton Wu2019-07-171-0/+1
* gallium: use MAP_DIRECTLY to mean supression of DISCARD in buffer_subdataMarek Olšák2019-07-151-4/+6
* gallium: get rid of PIPE_CAP_SM3Erik Faye-Lund2019-07-101-1/+3
* virgl: remove virgl_transfer_queue_listsChia-I Wu2019-07-092-36/+13
* virgl: simplify virgl_transfer_queue_extendChia-I Wu2019-07-091-34/+5
* virgl: remove transfer after transfer_writeChia-I Wu2019-07-091-2/+1
* virgl: improve virgl_transfer_queue_is_queuedChia-I Wu2019-07-091-30/+21
* virgl: fix transfers_intersect for mipmapsChia-I Wu2019-07-091-7/+2
* virgl: fix some false positives in transfers_overlapChia-I Wu2019-07-091-27/+86
* virgl: Hide internal virgl_resource functionsAlexandros Frantzis2019-07-062-166/+157
* virgl: Use virgl_resource_transfer_map for texturesAlexandros Frantzis2019-07-062-60/+4
* virgl: Use virgl_resource_transfer_map for buffersAlexandros Frantzis2019-07-061-79/+1
* virgl: Introduce virgl_resource_transfer_mapAlexandros Frantzis2019-07-062-0/+92
* virgl: Clear the valid buffer range when possibleAlexandros Frantzis2019-07-032-0/+24
* android: virgl: fix generated virgl_driinfo.h building rulesMauro Rossi2019-06-291-2/+8
* virgl: Don't allow creating staging pipe_resourcesAlexandros Frantzis2019-06-283-24/+8
* virgl: Use virgl_staging_mgrAlexandros Frantzis2019-06-286-57/+34
* virgl: Add tests for virgl_staging_mgrAlexandros Frantzis2019-06-283-0/+424
* virgl: Introduce virgl_staging_mgrAlexandros Frantzis2019-06-284-0/+230
* virgl: Store the virgl_hw_res for copy transfersAlexandros Frantzis2019-06-286-10/+19
* virgl: add VIRGL_DEBUG_XFERChia-I Wu2019-06-253-4/+9
* virgl: add VIRGL_DEBUG_SYNCChia-I Wu2019-06-253-1/+20
* virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLEChia-I Wu2019-06-252-8/+10
* android: virgl: fix libmesa_winsys_virgil_common build and dependenciesMauro Rossi2019-06-211-1/+1
* virgl: Add debug flag to bypass driconf to enable the BGRA tweaksGert Wollny2019-06-202-0/+8
* virgl: Add a tweak to set the value for emulated queries of GL_SAMPLES_PASSEDGert Wollny2019-06-205-1/+12
* virgl: Add tweak to apply a swizzle when drawing/blitting to a emulated BGRA ...Gert Wollny2019-06-205-0/+9
* virgl: Add driconf tweak for emulating BGRA surfaces on GLESGert Wollny2019-06-203-0/+10
* virgl: Add override for BGRA format to use swizzled SRGB formatGert Wollny2019-06-204-1/+27
* virgl: Add code to accept BGRx_SRGB as RGBx_SRGBGert Wollny2019-06-202-3/+23
* virgl: Add skeleton to evaluate cap and send tweaksGert Wollny2019-06-205-0/+31
* virgl: factor out format host bits checkGert Wollny2019-06-201-16/+17
View Lorry Controller Status