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* spirv: Remove outdated SPIR-V decoration warningsArcady Goldmints-Orlov2020-02-241-3/+2
| | | | | | | | | | | | | | spirv_to_nir warns if it encounters XFB decorations and errors if it encounters a Stream decoration with value other than 0, despite the fact that these decorations are in fact handled correctly. Fixes dEQP-VK.transform_feedback.simple.query_1_* Fixes: cd4a14be06 "spirv: Handle XFB variable decorations" Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3910> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3910> (cherry picked from commit 5f3cbbd958d14924dded0e0a0908127f6bfa006d)
* spirv: Fix glsl type assert in spir2nir.Bas Nieuwenhuizen2020-01-071-0/+4
| | | | | | | | | | Fixes: 624789e3708 "compiler/glsl: handle case where we have multiple users for types" Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 96c9483ccf5bc9116f7b754a0ccbc09097275083) Conflicts: src/compiler/spirv/spirv2nir.c
* spirv: Don't leak GS initialization to other stagesCaio Marcelo de Oliveira Filho2019-11-111-1/+2
| | | | | | | | | | | | | The stage specific fields of shader_info are in an union. We've likely been lucky that this value was either overwritten or ignored by other stages. The recent change in shader_info layout in commit 84a1a2578da ("compiler: pack shader_info from 160 bytes to 96 bytes") made this issue visible. Fixes: cf2257069cb ("nir/spirv: Set a default number of invocations for geometry shaders") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 087ecd9ca58a84cf85e66323b44140e7304d5f93)
* spirv: Don't fail if multiple ordering semantics bits are setCaio Marcelo de Oliveira Filho2019-10-291-9/+30
| | | | | | | | | | | | | | Vulkan requires that only one bit for the ordering is set, but old versions of GLSLang just set all the bits. This was fixed as part of https://github.com/KhronosGroup/glslang/commit/c51287d744fb6e7e9ccc09f6f8451e6c64b1dad6 but we can still find older versions (or shaders compiled with it) around. So instead of failing, emit a warning and fallback to the effective result of any combination of multiple bits: AcquireRelease. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2018 Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* util: rename list_empty() to list_is_empty()Timothy Arceri2019-10-281-1/+1
| | | | | | | This makes it clear that it's a boolean test and not an action (eg. "empty the list"). Reviewed-by: Eric Engestrom <eric@engestrom.ch>
* spirv: Add helper to find args of Image OperandsCaio Marcelo de Oliveira Filho2019-10-241-22/+79
| | | | | | | | | | | Avoid keeping track of the idx and all possible image operands for each operation. Note for convenience we split up the handling of ImageOperandsOffsetMask and ImageOperandsConstOffsetMask. Suggested by Jason Ekstrand. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Check that only one offset is defined as Image OperandCaio Marcelo de Oliveira Filho2019-10-241-0/+6
| | | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Add imageoperands_to_string helperCaio Marcelo de Oliveira Filho2019-10-242-3/+23
| | | | | | | | Change the information to also include the category, so that the particulars of BitEnum enumeration can be handled in the template. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Handle MakePointerAvailable/VisibleCaio Marcelo de Oliveira Filho2019-10-241-0/+32
| | | | | | | | | | | Emit barriers with semantics matching the access operand and the storage class of the pointer. v2: Fix order of visible / available emission relative to the operations. (Bas) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Handle MakeTexelAvailable/VisibleCaio Marcelo de Oliveira Filho2019-10-241-8/+39
| | | | | | | | | Set the memory semantics and scope for later emitting the barrier. Note the barrier emission code already exist in vtn_handle_image for the Image atomics. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Add option to emit scoped memory barriersCaio Marcelo de Oliveira Filho2019-10-242-0/+126
| | | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Add SpvMemoryModelVulkan and related capabilitiesCaio Marcelo de Oliveira Filho2019-10-241-3/+22
| | | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Emit memory barriers for atomic operationsCaio Marcelo de Oliveira Filho2019-10-242-1/+100
| | | | | | | | | | | | Add a helper to split the memory semantics into before and after the operation, and use that result to emit memory barriers. v2: Be more explicit about which bits we are keeping around when splitting memory semantics into a before and after. For now we are ignoring Volatile. (Jason) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Parse memory semantics for atomic operationsCaio Marcelo de Oliveira Filho2019-10-242-5/+38
| | | | | | | | Including the right storage memory semantic based on the storage class of the operation. These will be used later to emit memory barriers. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv/info: Add a memorymodel_to_string helperJason Ekstrand2019-10-242-0/+2
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* nir: Add new texop nir_texop_tex_prefetchEduardo Lima Mitev2019-10-181-0/+2
| | | | | | | | | | | | | | | | | | This is like nir_texop_tex, but signals that the sampling coordinates are immutable during the shader stage, in a way that allows the HW that supports pre-dispatching sampling operations to pre-fetch the result prior to scheduling the shader stage. This is introduced to support the feature in Freedreno. Adreno HW from a4xx supports it. A NIR pass introduced later in this series will detect sampling operations that are eligible for pre-dispatch, and replace nir_texop_tex by this new op, to tell the backend to enable pre-fetch. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* spirv: set correct dest_type for texture query opsJonathan Marek2019-10-151-7/+17
| | | | | Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* nir/builder: Move nir_atan and nir_atan2 from SPIR-V translatorNeil Roberts2019-10-121-153/+2
| | | | | | | Moves build_atan and build_atan2 into nir_builtin_builder. The goal is to be able to use this from the GLSL translator too. Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* spirv: Implement SPV_KHR_shader_clockCaio Marcelo de Oliveira Filho2019-10-071-0/+35
| | | | | | | We only have the subgroup variant in NIR (equivalent to clockARB), so only support that for now. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
* spirv: Add missing break for capability handlingCaio Marcelo de Oliveira Filho2019-09-181-0/+1
| | | | | | | New added cases "stole" the previous break. Fixes: 420ad0a1a3d ("spirv: check support for SPV_KHR_float_controls capabilities") Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
* nir: fix denorms in unpack_half_1x16()Samuel Iglesias Gonsálvez2019-09-171-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | According to VK_KHR_shader_float_controls: "Denormalized values obtained via unpacking an integer into a vector of values with smaller bit width and interpreting those values as floating-point numbers must: be flushed to zero, unless the entry point is declared with the code:DenormPreserve execution mode." v2: - Add nir_op_unpack_half_2x16_flush_to_zero opcode (Connor). v3: - Adapt to use the new NIR lowering framework (Andres). v4: - Updated to renamed shader info member and enum values (Andres). v5: - Simplify flags logic operations (Caio). Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> [v2]
* nir: add support for flushing to zero denorm constantsSamuel Iglesias Gonsálvez2019-09-171-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: - Refactor conditions and shared function (Connor). - Move code to nir_eval_const_opcode() (Connor). - Don't flush to zero on fquantize2f16 From Vulkan spec, VK_KHR_shader_float_controls section: "3) Do denorm and rounding mode controls apply to OpSpecConstantOp? RESOLVED: Yes, except when the opcode is OpQuantizeToF16." v3: - Fix bit size (Connor). - Fix execution mode on nir_loop_analize (Connor). v4: - Adapt after API changes to nir_eval_const_opcode (Andres). v5: - Simplify constant_denorm_flush_to_zero (Caio). v6: - Adapt after API changes and to use the new constant constructors (Andres). - Replace MAYBE_UNUSED with UNUSED as the first is going away (Andres). v7: - Adapt to newly added calls (Andres). - Simplified the auxiliary to flush denorms to zero (Caio). - Updated to renamed supported capabilities member (Andres). Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> [v4] Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* spirv/nir: keep track of SPV_KHR_float_controls execution modesSamuel Iglesias Gonsálvez2019-09-171-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: - Add support for rounding modes for each floating point bit size. v3: - Commit e68871f6a44 ("spirv: Handle constants and types before execution modes") changed when the execution modes are handled, which affects the result of the floating point constants when the rounding mode is set in the execution mode. Moved the handling of the rounding modes before we handle the constants. v4: - Rename vtn_decoration "literals" to "operands" (Andres). - Simplify execution mode parsing util function (Caio). - Extend the comment about the timing of the handling of the rounding modes (Caio). v5: - Correct extension name (Caio). - Rename shader info member (Andres). - Rename float controls enum (Andres). Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> [v3] Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* spirv: check support for SPV_KHR_float_controls capabilitiesSamuel Iglesias Gonsálvez2019-09-171-0/+7
| | | | | | | | | | v2: - Correct extension name (Caio). - Rename supported capabilities member (Andres). Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> [v1] Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* spirv: Handle ShaderLayer and ShaderViewportIndex capabilitiesCaio Marcelo de Oliveira Filho2019-09-161-0/+2
| | | | | | | | SPIR-V 1.5 incorported the SPV_EXT_shader_viewport_index_layer but splitting into the two capabilities above. Just handle them as we support the extension already. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* spirv: Update JSON and headers to 1.5Caio Marcelo de Oliveira Filho2019-09-162-73/+1005
| | | | Acked-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: Add explicit signs to image min/max intrinsicsJason Ekstrand2019-08-211-4/+4
| | | | | | | | | | | This better matches all the other atomic intrinsics such as those for SSBOs and shared variables where the sign is part of the intrinsic opcode. Both generators (GLSL and SPIR-V) know the sign from the type of the image variable or handle. In SPIR-V, signed min/max are separate opcodes from unsigned. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* spirv: Drop lower_workgroup_access_to_offsetsCaio Marcelo de Oliveira Filho2019-08-103-136/+14
| | | | | | | | Intel drivers are not using this anymore, and turnip still don't have Compute Shaders, so won't make a difference to stop using this option. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Rob Clark <robdclark@chromium.org>
* spirv: fixup signatureErik Faye-Lund2019-08-082-3/+3
| | | | | | | | | This avoids a warning on some compiler, complaining about implicitly casting the function-pointer. Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Fixes: d482a8f "spirv: Update the OpenCL.std.h header" Acked-by: Eric Engestrom <eric@engestrom.ch>
* nir/spirv: Fix gl_BaseVertex for non-indexed draws for OpenGLAntia Puentes2019-08-061-2/+5
| | | | | | | | | Lowers BaseVertex to the correct system value for OpenGL. v2: use options->environment rather than adding a new flag to spirv_to_nir_options Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* compiler: replace MAYBE_UNUSED with UNUSEDEric Engestrom2019-07-311-1/+1
| | | | | | | | MAYBE_UNUSED is going away, so let's replace legitimate uses of it with UNUSED, which the former aliased to so far anyway. Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* spirv: don't discard access set by vtn_pointer_dereferenceLionel Landwerlin2019-07-301-1/+1
| | | | | | | | | We can have a access flag already set here so just augment the existing ones. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 0fb61dfdeb ("spirv: propagate access qualifiers through ssa & pointer") Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* spirv: propagate access qualifiers through ssa & pointerLionel Landwerlin2019-07-263-4/+62
| | | | | | | | | | | | | | | | | | | | | | | | | Not only variables can be flagged as NonUniformEXT but also expressions. We're currently ignoring it in an expression such as : imageLoad(data[nonuniformEXT(rIndex)], 0) The associated SPIRV : OpDecorate %69 NonUniformEXT ... %69 = OpLoad %61 %68 This changes propagates access qualifiers through ssa & pointers so that when it hits a OpLoad/OpStore style instructions, qualifiers are not forgotten. Fixes failure the following tests : dEQP-VK.descriptor_indexing.* Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 8ed583fe523703 ("spirv: Handle the NonUniformEXT decoration") Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* spirv: wrap push ssa/pointer valuesLionel Landwerlin2019-07-264-69/+89
| | | | | | | | | | This refactor allows for common code to apply decoration on all ssa/pointer values. In particular this will allow to propagage access qualifiers. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Suggested-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* spirv: Fix order of barriers in SpvOpControlBarrierDaniel Schürmann2019-07-191-4/+4
| | | | | | | | Semantically, the memory barrier has to come first to wait for the completion of pending memory requests. Afterwards, the workgroups can be synchronized. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* spirv: Bail when we see CounterBuffer decorationCaio Marcelo de Oliveira Filho2019-07-161-1/+1
| | | | | | | This decoration can be ignored, so we can just skip the next steps. Otherwise we'd have to also handle it in apply_var_decoration. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* spirv: Add a warning for ArrayStride on arrays of blocksJason Ekstrand2019-07-161-2/+9
| | | | | | | | | | | It's disallowed according to the SPIR-V spec or at least I think that's what the spec says. It's in a section explicitly about explicit layout of things in the StorageBuffer, Uniform, and PushConstant storage classes so it's not 100% clear that it applies with other storage classes. However, it seems like it should apply in general and violating it can trigger (fairly harmless) asserts in NIR. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* spirv: Ignore ArrayStride for storage classes that should not use itCaio Marcelo de Oliveira Filho2019-07-151-4/+18
| | | | | | | | The stride was already overriden when using lower_workgroup_access_to_offsets, so elaborate a bit the commentary there. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* spirv: Fix stride calculation when lowering Workgroup to offsetsCaio Marcelo de Oliveira Filho2019-07-151-1/+1
| | | | | | | | | | | | Use alignment to calculate the stride associated with the pointer types. That stride is used when the pointers are casted to arrays. Note that size alone is not sufficient, e.g. struct { vec2 a; vec1 b; } will have element an element size of 12 bytes, but the stride needs to be 16 bytes to respect the 8 byte alignment. Fixes: 050eb6389a8 "spirv: Ignore ArrayStride in OpPtrAccessChain for Workgroup" Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* spirv: Implement SPV_EXT_demote_to_helper_invocationCaio Marcelo de Oliveira Filho2019-07-081-0/+26
| | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* spirv: Update the headers from latest Khronos masterCaio Marcelo de Oliveira Filho2019-07-082-164/+258
| | | | | | | This corresponds to 29c11140baaf9f7fdaa39a583672c556bf1795a1 in https://github.com/KhronosGroup/SPIRV-Headers. Acked-by: Jason Ekstrand <jason@jlekstrand.net>
* spirv: Add an option for making FragCoord a sysvalConnor Abbott2019-07-082-1/+11
| | | | | | | | | | On AMD, FragCoord should be a sysval because it is handled separately from all the other inputs. We were already doing this in radeonsi, but we weren't doing it with radv. It'll be much more annoying to handle VARYING_SLOT_POS in fragment shaders when we let NIR lower FS inputs for us, so here we add an option so that radv can get it as a system value. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Ignore ArrayStride in OpPtrAccessChain for WorkgroupCaio Marcelo de Oliveira Filho2019-07-021-4/+6
| | | | | | | | | | | | | | | | | From OpPtrAccessChain description in the SPIR-V spec (1.4 rev 1): For objects in the Uniform, StorageBuffer, or PushConstant storage classes, the element’s address or location is calculated using a stride, which will be the Base-type’s Array Stride when the Base type is decorated with ArrayStride. For all other objects, the implementation will calculate the element’s address or location. For non-CL shaders the driver should layout the Workgroup storage class, so override any explicitly set ArrayStride in the shader. This currently fixes only the lower_workgroup_access_to_offsets case, which is used by anv. Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
* spirv/nir: fill up nir variable info for ubos and ssboAlejandro Piñeiro2019-06-301-1/+3
| | | | | | | | | | | | | | | The data for some nir variables is only filled up for some specific modes. We need now too for UBO/SSBO, as such info would be used when linking for OpenGL (ARB_gl_spirv). There is an existing comment just before that code (starts with XXX) that points that binding still needs to be filled up for uniform variables at that point, and that should be fixed, although it doesn't specify why that's a problem or what would be the alternative. For now doing the same for UBO/SSBO, and will hope that the future fixing is done for all of them. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
* spirv/nir: create nir variable for UBO/SSBOAlejandro Piñeiro2019-06-301-2/+13
| | | | | | | | | | | | | | | | | | | | Providing nir variables for UBO/SSBO it is not required for Vulkan, but it is needed for OpenGL (ARB_gl_spirv), like for example, to gather info from the UBO/SSBO while linking. In opposite with most cases where the nir variables is created, here the type assigned is the full type (not just the bare type). This is needed because while linking using the nir shader we need the explicit layout info (explicit stride, explicit offset, row_major, etc). Also, we need to assign an interface type, used also on the OpenGL linker if it is a UBO/SSBO. See ir_variable::is_in_buffer_block as example. v2: assign interface_type to be the variable type, not need to be arrayness (Timothy) Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
* spirv: Implement NoSignedWrap and NoUnsignedWrap decorationsCaio Marcelo de Oliveira Filho2019-06-261-0/+33
| | | | | | | | | | | | | | | | When handling the specified ALU operations, check for the decorations and set nir_alu_instr no_signed_wrap and no_unsigned_wrap flags accordingly. v2: Add a glsl_base_type_is_unsigned_integer() helper. (Karol) v3: Rename helper to glsl_base_type_is_uint(). v4: Use two flags, so we don't need the helper anymore. (Connor) v5: Pass alu directly to handle function. (Jason) Reviewed-by: Karol Herbst <kherbst@redhat.com> [v3] Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* spirv: Restrict use of descriptor intrinsics to VulkanCaio Marcelo de Oliveira Filho2019-06-191-1/+8
| | | | | | | In ARB_gl_spirv we'll be able to use variables for uniform buffers, so don't use the descriptor intrinsics to lower the block access. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: Make nir_constant a vector rather than a matrixJason Ekstrand2019-06-193-69/+41
| | | | | | | | | | Most places in NIR, we treat matrices like arrays. The one annoying exception to this has been nir_constant where a matrix is a first-class thing. This commit changes that so a matrix nir_constant is the same as an array nir_constant. This makes matrix nir_constants a tiny bit more expensive but shrinks all others by 96B. Reviewed-by: Karol Herbst <kherbst@redhat.com>
* spirv: Only copy needed components for OpSpecConstantOpJason Ekstrand2019-06-191-1/+6
| | | | Reviewed-by: Karol Herbst <kherbst@redhat.com>
* spirv: Use a single path for OpSpecConstantOp of OpVectorShuffleJason Ekstrand2019-06-191-37/+19
| | | | | | | | | Now that nir_const_value is a scalar, there's no reason why we need multiple paths here and it's just extra paths to keep working. While we're here, we also add a vtn_fail_if check that component indices are in-bounds. Reviewed-by: Karol Herbst <kherbst@redhat.com>
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