summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
...
* gallium/swr: simplify environmental variabled expansion codeKrzysztof Raszkowski2020-02-142-30/+1
| | | | | | | | | | | | There were 2 versions of code doing the same thing. Since std::regexp are locale-sensitive better is to leave old good way to do this. Fixes: https://gitlab.freedesktop.org/mesa/mesa/issues/2520 Reviewed-by: Jan Zielinski <jan.zielinski@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3761> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3761> (cherry picked from commit 689817c9dfde9a0852f2b2489cb0fa93ffbcb215)
* glsl: fix gl_nir_set_uniform_initializers() for image arraysTimothy Arceri2020-02-142-2/+2
| | | | | | | | | | | | | | The if was incorrectly checking for an image type on what could be an array of images. Here we change it to use the type stored in uniform storage which has already been stripped of arrays, this is what the above code for samplers does also. Fixes: 2bf91733fcb5 ("nir/linker: Set the uniform initial values") Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757> (cherry picked from commit 676869e1d4bb1660430fcdb99443238a7de50eb8)
* .pick_status.json: Update to 946eacbafb47c8b94d47e7c9d2a8b02fff5a22faDylan Baker2020-02-141-0/+153
|
* iris: fix aux buf map failure in 32bits app on AndroidTapani Pälli2020-02-132-9/+10
| | | | | | | | | | Cc: mesa-stable@lists.freedesktop.org Reported-by: Zhifang Long <zhifang.long@intel.com> Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784> (cherry picked from commit fdd20be324eabab7da1ba67cf7e379398d771186)
* radeonsi: make si_fence_server_signal flush pipe without workPeng Huang2020-02-132-1/+5
| | | | | | | | | | | | glSignalSemaphoreEXT sometime doesn't signal the semaphore, it is because radeonsi doesn't flush if gl context doesn't have pending work. Fix the porblem by always submit ib. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3779> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3779> (cherry picked from commit 0660cbf4262891e6380faf0d99217b2d27873051)
* .pick_status.json: Update to 2a98cf3b2ecea43cea148df7f77d2abadfd1c9dbDylan Baker2020-02-131-0/+405
|
* docs: Add SHA256 sum for 19.3.4Dylan Baker2020-02-131-1/+1
|
* VERSION: bump version for 19.3.4mesa-19.3.4Dylan Baker2020-02-131-1/+1
|
* docs: Add release notes for 19.3.4Dylan Baker2020-02-131-0/+187
|
* nir: do not use De Morgan's Law rules for flt and fgeSamuel Pitoiset2020-02-112-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In presence of NaNs, "!(flt(a, b) && flt(c, d))" is NOT EQUAL to "fge(a, b) || fge(c, d)". These optimizations are unsafe for apps that rely on NaN behaviour. pipeline-db (GFX9/LLVM): Totals from affected shaders: SGPRS: 3176 -> 3136 (-1.26 %) VGPRS: 2188 -> 2144 (-2.01 %) Spilled SGPRs: 227 -> 169 (-25.55 %) Code Size: 150572 -> 151800 (0.82 %) bytes Max Waves: 307 -> 310 (0.98 %) pipeline-db (GFX9/ACO): Totals from affected shaders: SGPRS: 18744 -> 18744 (0.00 %) VGPRS: 15576 -> 15580 (0.03 %) Spilled SGPRs: 164 -> 164 (0.00 %) Code Size: 1573012 -> 1576492 (0.22 %) bytes Max Waves: 1534 -> 1532 (-0.13 %) Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2127 Fixes: d1ed4ffe0b7 ("nir: Use De Morgan's Law on logic compounded comparisons") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696> (cherry picked from commit 8e7728077435c5c5ad8c328761277f8ff3b32112)
* Revert "gallium: Fix big-endian addressing of non-bitmask array formats."Eric Anholt2020-02-112-18/+7
| | | | | | | | | | | | | | | | | | | | | | | | | This reverts the functional part of commit d17ff2f7f1864c81c1e00d04baf20f953c6d276a, leaving the unit test for mesa/pipe agreement on what's an array. The issue is that the util_channel_desc.shift values on array formats are not used for bit addressing in memory, they're bit addressing within a word treating a pixel of the format as a native type, as seen by llvmpipe's use of the values to do shifts (see lp_build_unpack_arith_rgba_aos() for example). This means the values are nonsensical for 3-byte RGB, but then llvmpipe doesn't expose those formats so it works out. I still want to clean up our big-endian format handling at some point, but let's fix the s390x regression first, sort out our format unit tests in CI, then be able to refactor with confidence. Fixes: d17ff2f7f186 ("gallium: Fix big-endian addressing of non-bitmask array formats.") Closes: #2472 Acked-by: Marek Olšák <marek.olsak@amd.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3721> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3721> (cherry picked from commit 1886dbfe7362baa221009371434f158b97183164)
* radeonsi: fix the DCC MSAA bug workaroundMarek Olšák2020-02-112-2/+2
| | | | | | | Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3646> (cherry picked from commit fbb27eebc8cab1a5d70ea67a37de8d18f20a88f0)
* svga: fix size of format_conversion_table[]Neha Bhende2020-02-112-1/+3
| | | | | | | | | | | Since we are now using sparse matrix for format_conversion_table, we have to make sure we have last entry in table which gives the sense of required size of format_conversion_table Fixes: 84db6ba7 ("svga: Drop unsupported formats from the format table") Reviewed-by: Charmaine Lee <charmainel@vmware.com> (cherry picked from commit 470e73e7f86b4530cf789a779f43674ecec91881)
* .pick_status.json: Update to 23037627359e739c42b194dec54875aefbb9d00bDylan Baker2020-02-111-0/+594
|
* Vulkan overlay: use the corresponding image index for each swapchainGeorg Lehmann2020-02-102-4/+9
| | | | | | | | | | | pImageIndices should be a pointer to the current image index otherwise every swapchain but the first one could have a wrong image index Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3741> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3741> (cherry picked from commit 7283c33b981f975361e3bfa62a339c88f2642cbb)
* freedreno/ir3: put the conversion back for half const to the right place.Hyunjun Ko2020-02-102-7/+7
| | | | | | | | | | | | | | The previous commit leads to match immed values unexpectedly. This makes constlen for each shader including bvert wrong. Also fixes atan2 for mediump deqp tests. Fixes: cbd1f47433b ("freedreno/ir3: convert back to 32-bit values for half constant registers.") v2: Move conversion up above fabs/fneg modifier handling as well. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737> (cherry picked from commit 260bd32b58a55ac0d9870497caef3a4602e19d47)
* .pick_status.json: Update to 689817c9dfde9a0852f2b2489cb0fa93ffbcb215Dylan Baker2020-02-101-0/+162
|
* Vulkan Overlay: Don't try to change the image layout to present twiceGeorg Lehmann2020-02-072-23/+28
| | | | | | | | | | | The render pass already does the transition. The pipeline barrier is still needed to transfer the queue family ownership. Fixes: 320b0f66c274 ("vulkan/overlay: bounce image back to present layout") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3740> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3740> (cherry picked from commit f239bb8020df4176ca539bafff327ab5c8da2c2e)
* Correctly wait in the fragment stage until all semaphores are signaledGeorg Lehmann2020-02-072-3/+11
| | | | | | | | | | | | This fixes two issues: - a crash if the application uses more than one semaphore for presenting because the driver expects one stage per semaphore - the swapchain image could be not ready yet if the semaphores aren't signaled, #946 is possible related Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3718> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3718> (cherry picked from commit 1c79afd94620925cb9e0903f24f91c3ab9ecfcb4)
* svga: Fix banded DMA uploadThomas Hellstrom2020-02-072-11/+12
| | | | | | | | | | | | | | | | | | | A previous commit ("winsys/svga: Limit the maximum DMA hardware buffer size") made banded DMA transfer kick in when transfering gnome-shell window contents under gnome-shell / wayland. This uncovered a bug where we assumed that banded DMA transfers always occur to the top (y=0) of the surface. Fix this by taking the destination y offset into account. Cc: 19.2 19.3 20.0 <mesa-stable@lists.freedesktop.org> Fixes: 287c94ea498 ("Squashed commit of the following:") Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3733> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3733> (cherry picked from commit 451cf228d53ba8f51beb3dcf04370e126fb7ccb6)
* intel: Load the driver even if I915_PARAM_REVISION is not found.Rafael Antognolli2020-02-072-2/+2
| | | | | | | | | | | | | | | | This param is only available starting on kernel 4.1. Use a default value of 0 if it is not found instead. v2: Update commit message (Lionel) Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Mark Janes <mark.a.janes@intel.com> Fixes: 96e1c945f2b ("i965: Move device info initialization to common Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727> (cherry picked from commit 4aa7af9e9a4c19e10afaf4a3c756e62cf4d352c3)
* swr: Fix GCC 4.9 checks.Vinson Lee2020-02-073-3/+3
| | | | | | | | Fixes: f0a22956be48 ("swr/rast: _mm*_undefined_* implementations for gcc<4.9") Fixes: e21fc2c62527 ("swr/rast: non-regex knob fallback code for gcc < 4.9") Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Jan Zielinski <jan.zielinski@intel.com> (cherry picked from commit deb2bbf57ec1d0660dd85b7080bf5ebeb10e8768)
* .pick_status.json: Update to d8bae10bfe0f487dcaec721743cd51441bcc12f5Dylan Baker2020-02-071-0/+477
|
* radeonsi: stop using the VM_ALWAYS_VALID flagPierre-Eric Pelloux-Prayer2020-02-063-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allocation all the bo as ALWAYS_VALID means they must all fit in memory (vram + gtt) at each command submission. This causes some trouble when the total allocated memory is greater than the available memory. Possible solutions: - being able to tag/untag a bo as ALWAYS_VALID: would require kernel changes - disable VM_ALWAYS_VALID when memory usage is more than a percentage of the available memory - disable VM_ALWAYS_VALID entirely v1 of this patch implemented option 2. v2 (this version) implements option 3. Related issues: - https://gitlab.freedesktop.org/drm/amd/issues/607 - https://gitlab.freedesktop.org/mesa/mesa/issues/1257 It also helps with some piglit tests (-t maxsize -t "max[_-].*size" -t maxuniformblocksize): instead of crashing the machine, the tests fail cleanly. (cherry-pick from ab54624d0d52d88da7fb7f4df61f33f600a1dfd7) Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3709> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3709>
* mesa: allow bit queries for EXT_disjoint_timer_queryTapani Pälli2020-02-051-4/+14
| | | | | | | | Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090 Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3707> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3707>
* mapi: add GetInteger64vEXT with EXT_disjoint_timer_queryTapani Pälli2020-02-053-1/+16
| | | | | | | | | | | | | | From EXT_disjoint_timer_query spec: "Interaction: This extension adds GetInteger64vEXT if OpenGL ES 3.0 is not supported" See https://github.com/KhronosGroup/OpenGL-Registry/issues/326. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090 Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3707>
* intel/fs: Don't count integer instructions as being possibly coissueIan Romanick2020-02-052-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integer instructions don't coissue. Before e64be391dd0 ("intel/compiler: generalize the combine constants pass"), this pass only looked at float sources. There's no shader-db data in that commit, so I collected some. The results are not good: Haswell total instructions in shared programs: 11898805 -> 11908127 (0.08%) instructions in affected programs: 1218680 -> 1228002 (0.76%) helped: 2 HURT: 5171 helped stats (abs) min: 12 max: 111 x̄: 61.50 x̃: 61 helped stats (rel) min: 1.59% max: 9.20% x̄: 5.40% x̃: 5.40% HURT stats (abs) min: 1 max: 311 x̄: 1.83 x̃: 1 HURT stats (rel) min: 0.02% max: 9.91% x̄: 1.05% x̃: 0.70% 95% mean confidence interval for instructions value: 1.55 2.05 95% mean confidence interval for instructions %-change: 1.02% 1.08% Instructions are HURT. total cycles in shared programs: 221664974 -> 221404750 (-0.12%) cycles in affected programs: 120012620 -> 119752396 (-0.22%) helped: 3464 HURT: 3159 helped stats (abs) min: 1 max: 428160 x̄: 314.55 x̃: 16 helped stats (rel) min: <.01% max: 57.33% x̄: 3.40% x̃: 1.28% HURT stats (abs) min: 1 max: 87846 x̄: 262.54 x̃: 14 HURT stats (rel) min: <.01% max: 85.57% x̄: 3.01% x̃: 0.77% 95% mean confidence interval for cycles value: -224.23 145.65 95% mean confidence interval for cycles %-change: -0.50% -0.19% Inconclusive result (value mean confidence interval includes 0). total spills in shared programs: 9804 -> 10047 (2.48%) spills in affected programs: 6869 -> 7112 (3.54%) helped: 2 HURT: 41 total fills in shared programs: 19863 -> 20319 (2.30%) fills in affected programs: 17428 -> 17884 (2.62%) helped: 2 HURT: 41 LOST: 20 GAINED: 13 This also prevents regressions in "intel/fs: Promote integer constants after lowering integer multiplication" (note: that patch will probably not be committed). When the passes are reorderd, code like mul(8) acc0<1>D g9<8,8,1>D -2078209981D { align1 1Q }; gets turned into mov(1) g23<1>D 2078209981D { align1 WE_all 1N }; ... mul(8) acc0<1>D g13<8,8,1>D -g23<0,1,0>D { align1 1Q compacted }; It's not 100% clear why, but these produce different results. Note that -2078209981 & 0x0ffff = 0x0843, and -(2078209981 & 0x0ffff) = 0xffff0843. It seems like the upper 16-bits of the negation should be ignored. Fixes: e64be391dd0 ("intel/compiler: generalize the combine constants pass") Cc: Iago Toral Quiroga <itoral@igalia.com> Suggested-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com> The shaders with spills or fills hurt are the usual suspects. A couple compute shaders in Dirt Showdown and a compute shader in Bioshock Infinite. On Haswell, a compute shader (that appears twice in shader-db) from Aztec Ruins was also hurt for spill and fills. Haswell total instructions in shared programs: 11573934 -> 11568335 (-0.05%) instructions in affected programs: 828623 -> 823024 (-0.68%) helped: 2825 HURT: 6 helped stats (abs) min: 1 max: 134 x̄: 2.16 x̃: 1 helped stats (rel) min: 0.02% max: 9.05% x̄: 0.84% x̃: 0.61% HURT stats (abs) min: 1 max: 216 x̄: 81.83 x̃: 56 HURT stats (rel) min: 0.16% max: 8.65% x̄: 4.21% x̃: 4.68% 95% mean confidence interval for instructions value: -2.31 -1.64 95% mean confidence interval for instructions %-change: -0.85% -0.80% Instructions are helped. total cycles in shared programs: 187573593 -> 187004633 (-0.30%) cycles in affected programs: 82816107 -> 82247147 (-0.69%) helped: 2186 HURT: 1741 helped stats (abs) min: 1 max: 35230 x̄: 326.96 x̃: 16 helped stats (rel) min: <.01% max: 46.11% x̄: 3.11% x̃: 0.90% HURT stats (abs) min: 1 max: 6138 x̄: 83.73 x̃: 16 HURT stats (rel) min: <.01% max: 104.11% x̄: 2.73% x̃: 0.75% 95% mean confidence interval for cycles value: -197.13 -92.64 95% mean confidence interval for cycles %-change: -0.72% -0.33% Cycles are helped. total spills in shared programs: 7870 -> 7743 (-1.61%) spills in affected programs: 2260 -> 2133 (-5.62%) helped: 31 HURT: 5 total fills in shared programs: 6320 -> 6263 (-0.90%) fills in affected programs: 3547 -> 3490 (-1.61%) helped: 31 HURT: 6 LOST: 9 GAINED: 9 Ivybridge total instructions in shared programs: 11863372 -> 11859793 (-0.03%) instructions in affected programs: 757183 -> 753604 (-0.47%) helped: 2236 HURT: 3 helped stats (abs) min: 1 max: 81 x̄: 1.86 x̃: 1 helped stats (rel) min: 0.03% max: 5.26% x̄: 0.74% x̃: 0.48% HURT stats (abs) min: 11 max: 301 x̄: 192.33 x̃: 265 HURT stats (rel) min: 1.55% max: 10.51% x̄: 6.89% x̃: 8.62% 95% mean confidence interval for instructions value: -2.01 -1.18 95% mean confidence interval for instructions %-change: -0.77% -0.70% Instructions are helped. total cycles in shared programs: 178377378 -> 177946087 (-0.24%) cycles in affected programs: 76261390 -> 75830099 (-0.57%) helped: 1635 HURT: 1395 helped stats (abs) min: 1 max: 34796 x̄: 333.53 x̃: 16 helped stats (rel) min: <.01% max: 47.15% x̄: 2.82% x̃: 0.64% HURT stats (abs) min: 1 max: 4315 x̄: 81.74 x̃: 18 HURT stats (rel) min: <.01% max: 49.98% x̄: 1.99% x̃: 0.53% 95% mean confidence interval for cycles value: -197.06 -87.62 95% mean confidence interval for cycles %-change: -0.78% -0.43% Cycles are helped. total spills in shared programs: 4188 -> 4182 (-0.14%) spills in affected programs: 1557 -> 1551 (-0.39%) helped: 30 HURT: 3 total fills in shared programs: 5056 -> 5245 (3.74%) fills in affected programs: 2708 -> 2897 (6.98%) helped: 30 HURT: 3 LOST: 5 GAINED: 1 No shader-db changes on any other Intel platform. Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544> (cherry picked from commit 59488cbbaca1268841fe5ba42d0a1202b33be23b)
* radv: Do not set SX DISABLE bits for RB+ with unused surfaces.Bas Nieuwenhuizen2020-02-052-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The extra bits in CB_SHADER_MASK break dual source blending in SkQP on a Stoney device. However: - As far as I can tell, some other dual source blend tests are passing before and after the change. - A hacked around skqp passes on my Vega desktop and Raven laptop - Getting Skqp to give any useful info or to run it outside of Android on ChromeOS is proving difficult. I have confirmed 3 strategies that seem to work: - The old radv behavior of setting CB_SHADER_MASK to 0xF - AMDVLK: CB_SHADER_MASK = 0xFF, and the 3 RB+ regs are 0. - radeonsi: CB_SHADER_MASK = 0xFF, but does not set DISABLE bits in SX_BLEND_OPT_CONTROL for CB 1-7. Let us use the radeonsi solution as that solution also seems like the correct thing to do for holes. I have tested on my Raven laptop that setting the high surfaces to not disabled and downconvert to 32_R does not imply a performance penalty. Fixes: e9316fdfd48 "radv: fix setting CB_SHADER_MASK for dual source blending" Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670> (cherry picked from commit 65a6dc5139fddd5e01eaedcc57fc67e0a6a28c94)
* st/mesa: Handle the rest renderbuffer formats from OSMesaDanylo Piliaiev2020-02-052-1/+6
| | | | | | | | | | | Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2189 Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/989 Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2036 CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Eric Anholt <eric@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216> (cherry picked from commit d83abf1d378be059b4f41a6a44a9bf24c7394084)
* i965: Do not set front_buffer_dirty if there is no front bufferDanylo Piliaiev2020-02-052-2/+4
| | | | | | | | | | | | | | | | | | | Otherwise there will be a warning: "libEGL warning: FIXME: egl/x11 doesn't support front buffer rendering." Happens with EGL_KHR_surfaceless_context: eglMakeCurrent(egl_display, EGL_NO_SURFACE, EGL_NO_SURFACE, egl_context) eglMakeCurrent(egl_display, egl_surface, egl_surface, egl_context) glFlush() // Here will be a warning Cc: <mesa-stable@lists.freedesktop.org> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1525 Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628> (cherry picked from commit 36126b6211f1ac2da0aa94411608b2320553dbb6)
* .pick_status.json: Mark ca6a22305b275b49fbc88b8f4cba2fefb24c2a5d as backportedDylan Baker2020-02-051-1/+1
|
* .pick_status.json: Update to 7eaf21cb6f67adbe0e79b80b4feb8c816a98a720Dylan Baker2020-02-051-0/+495
|
* winsys/amdgpu: Close KMS handles for other DRM file descriptionsMichel Dänzer2020-02-042-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | When a BO or amdgpu_screen_winsys is destroyed. Should fix leaking such BOs in other DRM file descriptions. v2: * Pass the correct file descriptor to drmIoctl (Pierre-Eric Pelloux-Prayer) * Use _mesa_hash_table_remove v3: * Close handles in amdgpu_winsys_unref as well v4: * Adapt to amdgpu_winsys::sws_list_lock. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2270 Fixes: 11a3679e3aba "winsys/amdgpu: Make KMS handles valid for original DRM file descriptor" Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (Cherry picked from commit ca6a22305b275b49fbc88b8f4cba2fefb24c2a5d) Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
* winsys/amdgpu: Re-use amdgpu_screen_winsys when possibleMichel Dänzer2020-02-042-24/+48
| | | | | | | | | | | | | | | | | | | Namely, if os_same_file_description determined that the DRM file descriptor references the same file description. v2: * Adapt to amdgpu_winsys::sws_list_lock. v3: * Fix comparison of amdgpu_screen_winsys file descriptions, see https://gitlab.freedesktop.org/mesa/mesa/issues/2413 . * Lock amdgpu_winsys::sws_list_lock for traversing the sws_list in amdgpu_winsys_create. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (Cherry picked from commit 9f2bed49d476a15af0df270307f9051d810ea0ab) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
* util: Add os_same_file_description helperMichel Dänzer2020-02-042-0/+31
| | | | | | | Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (Cherry picked from commit f76cbc7901f7d500f5a4f74aedfd29970d1efd00) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
* winsys/amdgpu: Only re-export KMS handles for different DRM FDsMichel Dänzer2020-02-043-11/+32
| | | | | | | | | | | | | | | When the amdgpu_screen_winsys uses the same FD as the amdgpu_winsys (which is always the case for the first amdgpu_screen_winsys), we can just use bo->u.real.kms_handle. v2: * Also only create the kms_handles hash table if the amdgpu_screen_winsys fd is different from the amdgpu_winsys one. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (Cherry picked from commit c6468f66c7a47f0e16df2f1200db33eef6d2d1f4) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
* winsys/amdgpu: Keep track of retrieved KMS handles using hash tablesMichel Dänzer2020-02-043-0/+47
| | | | | | | | | | | | | | | | | | | | | | The assumption being that KMS handles are only retrieved for relatively few BOs, so hash tables should be efficient both in terms of performance and memory consumption. We use the address of struct amdgpu_winsys_bo as the key and its kms_handle field (the KMS handle valid for the DRM file descriptor passed to amdgpu_device_initialize) as the hash value. v2: * Add comment above amdgpu_screen_winsys::kms_handles (Pierre-Eric Pelloux-Prayer) v3: * Protect kms_handles hash table with amdgpu_winsys::sws_list_lock mutex. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (Cherry picked from commit 24075ac60fcc09dad173cb792e8f186c6379c086) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
* winsys/amdgpu: Keep a list of amdgpu_screen_winsyses in amdgpu_winsysMichel Dänzer2020-02-042-1/+28
| | | | | | | | | | v2: * Add dedicated mutex for the list. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (Cherry picked from commit f4010a6da9720b1593ca34faf0d8722ca85ed6c2) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
* etnaviv: Destroy rsc->pending_ctx set in etna_resource_destroy()Marek Vasut2020-02-042-1/+2
| | | | | | | | | | | | | | Destroy rsc->pending_ctx set in etna_resource_destroy(), otherwise the memory is allocated, never free'd, and becomes unreachable. This fixes a memory leak. Fixes: 9e672e4d20fb ("etnaviv: keep references to pending resources") Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633> (cherry picked from commit c32bd325e7688c781b7e5de58a2d0534c82f00a0)
* clover: Use explicit conversion from llvm::StringRef to std::stringJan Vesely2020-02-043-3/+4
| | | | | | | | | | Fixes build after llvm 777180a32b61070a10dd330b4f038bf24e916af1 ("[ADT] Make StringRef's std::string conversion operator explicit") CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Francisco Jerez <currojerez@riseup.net> (cherry picked from commit 0ccda2ebff83816cecf4dcb48f367a0d5c8f5fb1)
* .pick_status.json: Update to 9afdcd64f2c96f3fcc1a28912987f2e8066aa995Dylan Baker2020-02-041-0/+180
|
* panfrost: Fix the damage box clamping logicBoris Brezillon2020-02-032-1/+3
| | | | | | | | | | | | | When the rendering are is not covering the whole FBO, and the biggest damage rect is empty, we can have damage.max{x,y} > damage.min{x,y}, which leads to invalid reload boxes. Fixes: 65ae86b85422 ("panfrost: Add support for KHR_partial_update()") Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676> (cherry picked from commit b550b7ef3b8d12f533b67b1a03159a127a3ff34a)
* anv/blorp: Use the correct size for vkCmdCopyBufferToImageJason Ekstrand2020-02-032-1/+9
| | | | | | | | | | | | | | Now that we're using an uncompressed format for the buffer, we have to scale down the dimensions we pass into BLORP when doing buffer->image copies. Fixes: dd92179a72 "anv: Canonicalize buffer formats for image/buffer..." Closes: #2452 Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664> (cherry picked from commit d7fe9af6202413aa4e6f0f53d89577ed8ea80027)
* intel/fs: Write the address register with NoMask for MOV_INDIRECTJason Ekstrand2020-02-032-1/+10
| | | | | | | | | | | | This fixes a hang in the following Vulkan CTS test on TGL-LP: dEQP-VK.descriptor_indexing.storage_buffer_dynamic_in_loop Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642> (cherry picked from commit f93dfb509cbf9474befae9919dd8c135bbd67093)
* genxml: Add a new 3DSTATE_SF field on gen12Jason Ekstrand2020-02-032-1/+6
| | | | | | | | Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454> (cherry picked from commit 9da9abf8a7a605cc9b79bd4240ff715b79ac774a)
* anv,iris: Set 3DSTATE_SF::DerefBlockSize to per-poly on Gen12+Jason Ekstrand2020-02-034-2/+14
| | | | | | | | | | | | According to the BSpec, this should prevent hangs when using shaders with large URB entries. A more precise fix can be done but it requires re-arranging URB setup. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454> (cherry picked from commit e1bdb127b6875df602bd736465d597725f326621)
* .pick_status.json: Update to b550b7ef3b8d12f533b67b1a03159a127a3ff34aDylan Baker2020-02-031-0/+720
|
* bin/pick-ui: Add a new maintainer script for picking patchesDylan Baker2020-02-035-0/+1129
| | | | | | | | | In the long term the goal of this script is to nearly completely automate the process of picking stable nominations, in a well tested way. In the short term the goal is to provide a better, faster UI to interact with stable nominations.
* radeonsi: disable display DCCPierre-Eric Pelloux-Prayer2020-02-031-2/+5
| | | | | | | | Display DCC needs https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2836 to work correctly. Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3440> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3440>
* anv: Improve BTI change cache flushingJason Ekstrand2020-02-033-1/+29
| | | | | | | | | | | | | | | | | | | This commit makes two changes: 1. We set pending_pipe_bits instead of emitting PIPE_CONTROL directly for the flush at the end of cmd_buffer_begin_subpass. 2. Because BLORP ops such as vkCmdClearAttachments may come in the middle of a render pass, we have to also flag the need for a cache flush after the blorp op. Fixes: 185630c6bc97 "anv/blorp: Do the gen11 BTI flush" Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547> (cherry picked from commit c70a786c77370bbc47f71a9f529d50116fd511da) Conflicts: src/intel/vulkan/genX_cmd_buffer.c
View Lorry Controller Status