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* intel/perf: improve dynamic loading config detectionstaging/19.0Lionel Landwerlin2019-06-211-16/+3
| | | | | | | | | | | | | | | | We're currently trying to detect dynamic loading config support by trying to remove to test config (hard coded in the i915 driver) and checking we get ENOENT. This can fail if the test config was updated in Mesa but not yet in i915. A better way to do this is to pick an invalid ID and check for ENOENT. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit c1621274401b4bd2de7db1f7a813f6bfce8307f8)
* intel/perf: fix EuThreadsCount value in performance equationsLionel Landwerlin2019-06-211-2/+1
| | | | | | | | | | EuThreadsCount is supposed to be the number of threads per EU, not the total number of threads in the whole device. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 1fc7b951278428 ("i965: Add Gen8+ INTEL_performance_query support") Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 0430c6d18a90549b1dd40ea29a0c28d1a8e3a47d)
* virgl: Assume sRGB write control for older guest kernels or virglrenderer hostsGert Wollny2019-06-211-1/+2
| | | | | | | | | | | | | | | | | When the host virglrenderer is an older version that doesn't check the sRGB write control feature, or when the guest kernel doesn't support CAPS v2, then the guest will only report support for GL 2.1 on a GL 3.3 host, even though it was supporting 3.3 with earlier guest mesa versions. By also checking the host feature check version this regression can be avoided. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110921 Fixes: 2845939d6a72 virgl: Set sRGB write control CAP based on host capabilities Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Chia-I Wu <olvaffe@gmail.com> (cherry-picked from commit 2b87753a84da7a1bd8a84f26f3cd0e03cc52c930)
* virgl: Add a caps feature check versionGert Wollny2019-06-212-0/+2
| | | | | | | | | | | | | | | | When we add new feature checks on the host side that is used to enable a cap conditionally that was enabled unconditionally before we might end up with a feature regression when a new mesa version is used with an old virglrenderer version that doesn't check for that cap. To work around this problem add a version id to the caps that corresponds to the features that are actually checked on the host and check that version too when enabling the cap. Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Pohsien Wang <pwang@chromium.org> (cherry-picked from commit a0edceb00dbe4771267615593f416a0dc9ccd52a)
* cherry-ignore: add additional 19.1 only patchesDylan Baker2019-06-201-0/+1
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* meson: Allow building radeonsi with just the android platform.Bas Nieuwenhuizen2019-06-201-3/+3
| | | | | | | | Just as was allowed by autotools. Fixes: 108d257a168 "meson: build libEGL" Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit d1c04835ab273c5f9806fbe2095b1dd03f460833)
* anv: Fix vulkan build in meson.Bas Nieuwenhuizen2019-06-201-1/+7
| | | | | | | | Apparently the android part was never ported to meson. CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 755c633b8d9c15227ad07bbc98f06627d4ecf55d)
* radv: Fix vulkan build in meson.Bas Nieuwenhuizen2019-06-201-0/+7
| | | | | | | | Apparently the android part was never ported to meson. CC: <mesa-stable@lists.freedesktop.org> Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 4c300bd328138949659892447e7e68028cc950cb)
* radv: fix FMASK expand with SRGB formatsSamuel Pitoiset2019-06-201-1/+2
| | | | | | | | | Found while working on DCC for MSAA. Fixes: 6b976024a87 ("radv: add support for FMASK expand") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit a7f75377aba6853e08561acb9609c5e262e4d9a6)
* egl: Don't add hardware device if there is no render node v2.Mathias Fröhlich2019-06-201-2/+2
| | | | | | | | | | | | | | | | Do not offer a hardware drm backed egl device if no render node is available. The current implementation will fail on this egl device. On top it issues a warning that is actually missleading. There are finally more error paths that can fail on the way to a hardware backed egl device. Fixing all of them would kind of require opening the drm device and see if there is a usable driver associated with the device. The taken approach avoids a full probe and fixes at least this kind of problem on kvm virtualization hosts I observe here. Fixes: dbb4457d985 ("egl: add EGL_EXT_device_drm support") Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de> (cherry picked from commit 5743a36b2b32a91eaf82c8d109932fe4fea01233)
* glsl: Fix out of bounds read in shader_cache_read_program_metadataKenneth Graunke2019-06-201-3/+2
| | | | | | | | | | | | | | | | | | | The VaryingNames array has NumVaryings entries. But BufferStride is a small array of MAX_FEEDBACK_BUFFERS (4) entries. Programs with more than 4 varyings would read out of bounds. Also, BufferStride is set based on the shader itself, which means that it's inherently already included in the hash, and doesn't need to be included again. At the point when shader_cache_read_program_metadata is called, the linker hasn't even set those fields yet. So, just drop it entirely. Fixes valgrind errors in KHR-GL45.transform_feedback.linking_errors_test. Fixes: 6d830940f78 glsl/shader_cache: Allow shader cache usage with transform feedback Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit 3c10a2726bcf686f03e31e79e40786e3894ff063)
* anv: Set STATE_BASE_ADDRESS upper bounds on gen7Jason Ekstrand2019-06-201-0/+17
| | | | | | | | | | This should fix floating-point border color on all gen7 HW. Integer is still thoroughly busted on gen7 because it doesn't exist on IVB and it's crazy on HSW. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 9672b7044cc329b94a72de9ec5bdda1895901304)
* radv: Decompress DCC when the image format is not allowed for buffers.Bas Nieuwenhuizen2019-06-203-2/+40
| | | | | | | | | | | Otherwise the buffer loads/stores in the bufimage meta operations fail. If we decompress DCC then we can use the "canonical" format compatible with the not-supported format. CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 410759091173fa61436ba46baeb20a79d5767849)
* i965: support UYVY for external import onlyHaihao Xiang2019-06-201-1/+2
| | | | | | | | | It is similar with YUYV Fixes: 165e704719b85c ("i965/i915: Add UYVY as the supported format") Signed-off-by: Haihao Xiang <haihao.xiang@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 8ead5bebdb5cedc5250116403166279b1b292a85)
* st/mesa: Add rgbx handling for fp formatsKevin Strasser2019-06-201-0/+6
| | | | | | | | | | Add missing cases for fp32 and fp16 formats. Fixes: c68334ffc0a9 "st/mesa: add floating point formats in st_new_renderbuffer_fb()" Signed-off-by: Kevin Strasser <kevin.strasser@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 845ec8576a600ea54f80a2639e0466041f145ffa)
* gallium/winsys/kms: Fix dumb buffer bppKevin Strasser2019-06-201-1/+1
| | | | | | | | | | | | | | The bpp in the dumb buffer creation request is hardcoded to 32, which is an incorrect assumption as the caller is free to pick any pipe format. Use the bpp supplied to us through util_format_get_blocksizebits(). Fixes: 3b176c441b "gallium: Add a dumb drm/kms winsys backed swrast provider" Signed-off-by: Kevin Strasser <kevin.strasser@intel.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit ec0a68e50dd3ebfbeee77670d7d09184d0907ead)
* radv: fix VK_EXT_memory_budget if one heap isn't availableSamuel Pitoiset2019-06-201-27/+33
| | | | | | | | | | | | When the visible VRAM size is equal to the VRAM size only two heaps are exposed. This fixes dEQP-VK.api.info.device.memory_budget. Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit d3781512468aa1c96e92cc6a99963cd0fed80d30)
* radv: fix occlusion queries on VegaMSamuel Pitoiset2019-06-201-21/+27
| | | | | | | | | | | | | | | The number of render backends is 16 but the enabled mask is 0xaaaa. As noticed by Bas, allowing disabled render backends might break the OCCLUSION_QUERY packet. We don't use it yet but keep this in mind. This fixes dEQP-VK.query_pool.* and dEQP-VK.multiview.*. Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 2ef9d2738c8905cb3a83baf14cc1d088786d57e3)
* radv: Prevent out of bound shift on 32-bit builds.Bas Nieuwenhuizen2019-06-201-2/+2
| | | | | | | | | uintptr_t is 32-bits then and shifting it by 32 bits results in undefined behavior IIRC. Fixes: b3c8de1c55c "radv: save all descriptor pointers into the trace BO" Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 39c71e002561052d0596200b2d0ebdb8cc39d862)
* radv: fix setting CB_SHADER_MASK for dual source blendingSamuel Pitoiset2019-06-201-2/+5
| | | | | | | | | | | | CB_SHADER_MASK was computed without the second color buffer format which looks totally wrong to me. While we are at it, copy a comment from RadeonSI. Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit e9316fdfd4899c269a19e106a6ffa4309ae48b27)
* mapi: correctly handle the full offset tableEmil Velikov2019-06-202-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Earlier commit converted ES1 and ES2 to a new, much simpler, dispatch generator. At the same time, GL/glapi and the driver side are still using the old code. There is a hidden ABI between GL*.so and glapi.so, former referencing entry-points by offset in the _glapi_table. Hence earlier commit added the full table of entry-points, alongside a marker for other cases like indirect GL(X) and driver-size remapping. Yet the patches did not handle things fully, thus it was possible to get different interpretations of the dispatch table after the marker. This commit fixes that adding an indicative error message to catch future bugs. While here correct the marker (MAX_OFFSETS) comment. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110302 Fixes: cf317bf0937 ("mapi: add all _glapi_table entrypoints tostatic_data.py") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit a379b1c0ee31a792bba250cc466ad4b161a610ec)
* radv: fix alpha-to-coverage when there is unused color attachmentsSamuel Pitoiset2019-06-201-1/+1
| | | | | | | | | | | | | When alphaToCoverage is enabled, we should always write the alpha channel of MRT0 if it's unused. This now matches RadeonSI. This fixes the new CTS: dEQP-VK.pipeline.multisample.alpha_to_coverage_unused_attachment.samples_*.alpha_invisible Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl (cherry picked from commit 91aa25f4625014ddf194578fc1c1d0a505e5f8db)
* anv/cmd_buffer: Initalize the clear color struct for CNL+Nanley Chery2019-06-201-13/+7
| | | | | | | | | | | | | | | On CNL+, the clear color struct is composed of RGBA channel values and fields which are either reserved by the HW or used to control fast-clears. Currently anv initializes the channel values to zero and allows the other fields to be undefined. Satisfy the MBZ field requirements by removing an optimization that doesn't hold true for CNL+ and pulling in the number of dwords to initialize from ISL. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit b4198e792c037dccb4d433abc1368bd8cc8d22ee)
* svga: Remove unnecessary check for the pre flush bit for setting vertex buffersCharmaine Lee2019-06-201-4/+4
| | | | | | | | | | | This fixes the missing rebind when the can_pre_flush bit is not set and the vertex buffers are the same as what have been sent. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Neha Bhende <bhenden@vmware.com> Signed-off-by: Charmaine Lee <charmainel@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> (cherry picked from commit f29b8fde915728134b2e2b912642fe573d405fcb)
* winsys/svga/drm: Fix 32-bit RPCI send messageDeepak Rawat2019-06-201-12/+23
| | | | | | | | | | | | | | | | | | | | | | Depending on whether compiled with frame-pointer or not, the temporary memory location used for the bp parameter in these macros are referenced relative to the stack pointer or the frame pointer. Hence we can never reference that parameter when we've modified either the stack pointer or the frame pointer, because then the compiler would generate an incorrect stack reference. Fix this by pushing the temporary memory parameter on a known location on the stack before modifying the stack- and frame pointers. Also in case of failuire RPCI channel is not closed which lead to vmx running out of channels. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> (cherry picked from commit 72fc886826e97a547828da427e1a157b83ba5ea0)
* anv: Fix check for isl_fmt in assertNataraj Deshpande2019-06-201-1/+1
| | | | | | | | | | | Checking isl_fmt returned value in assert seems appropriate instead of format variable. Fixes: f1654fa7e31 "anv/android: support creating images from external format" Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> (cherry picked from commit d6724471a5775cbbeaafff1e1982f322b1d04c94)
* nir/propagate_invariant: Don't add NULL vars to the hash tableJason Ekstrand2019-06-201-1/+10
| | | | | | | | Fixes: 8410cf66d "nir/propagate_invariant: Skip unknown vars" Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit d96878a66a559f6690f01e82f06fcf92ae958d3c)
* docs: Add SHA256 sums for 19.0.6Dylan Baker2019-06-051-1/+2
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* docs: Add relnotes for 19.0.6mesa-19.0.6Dylan Baker2019-06-051-0/+152
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* VERSION: bump to 19.0.6Dylan Baker2019-06-051-1/+1
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* winsys/drm: Fix out of scope variable usageDeepak Rawat2019-06-051-12/+13
| | | | | | | | | | | In this particular instance, struct member were used outside of the block where it was defined. Fix this by moving the definition outside of block. Signed-off-by: Deepak Rawat <drawat@vmware.com> Fixes: 569f83898768 ("winsys/svga: Add support for new surface ioctl, multisample pattern") Reviewed-by: Brian Paul <brianp@vmware.com> (cherry picked from commit 828e1b0b4c5eef96a7f9a64010532263430e1f13)
* egl/dri: flesh out and use dri2_create_drawable()Emil Velikov2019-06-057-60/+41
| | | | | | | | | | | | | | | | | | | | Wrap the loader->createNewDrawable() dance into a helper and use it throughout the codebase. This addresses a cases like surfaceless (SL) on swrast (SL on kms_swrast is fine) where we'd attempt using the wrong driver and crash out. v2: fixup quirky GBM (Mathias) v3: fixup GBM for real (Marek) Cc: mesa-stable@lists.freedesktop.org Cc: Mathias Fröhlich <Mathias.Froehlich@web.de> Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de> (v1) Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1) Signed-off-by: Emil Velikov <emil.velikov@collabora.com> (v2) Signed-off-by: Marek Olšák <marek.olsak@amd.com> (v2) Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 2282ec0ad6581b588f7bdde1211357123316b4b9)
* ac: fix a typo in ac_build_wg_scan_bottomMarek Olšák2019-06-051-1/+1
| | | | | | Cc: 19.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit c9b64b58dee89ac78d38358f7ebd75cf0d6b86dd)
* gallium: wrap u_screen in extern "C" for c++Dylan Baker2019-06-041-0/+8
| | | | | Some drivers (notabily SWR) are written in C++, and as such they need access to C headers with extern "C". So lets add that.
* gallium/aux: add PIPE_CAP_MAX_VARYINGS to u_screenAlok Hota2019-06-041-0/+3
| | | | | | | | Allows drivers using `u_pipe_screen_get_param_defaults` to use a fallback value for the new pipe cap. Default value of 8 based on GL 2.1 MAX_VARYING_FLOATS Reviewed-by: Eric Anholt <eric@anholt.net>
* gallium/swr: Param defaults for unhandled PIPE_CAPsAlok Hota2019-06-041-4/+3
| | | | | | | Without using this function, we fail the -Wswitch flag when compiling the default debugoptimized mode in Meson Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
* cherry-ignore: add another 19.1 only patchDylan Baker2019-06-041-0/+1
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* radv: do not use gfx fast depth clears for layered depth/stencil imagesSamuel Pitoiset2019-06-041-0/+1
| | | | | | | | | | | The driver should only fast depth clears with the graphics path when the view covers all image layers, otherwise this might corrupt layers when HTILE is enabled. Cc: 19.0 19.1 mesa-stable@lists.freedesktop.org Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 8a35eb0602735194f2976000ddff9dca2c8b5741)
* intel/compiler: Fix assertions in brw_alu3Sagar Ghuge2019-06-041-3/+3
| | | | | | | | | | v2: Fix assertion for src1 (Ian Romanick) Fixes: 3b967e17 (intel/compiler: Avoid false positive assertions) Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Suggested-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 3016756398c988e965ed189cfd99dc94ddb16626)
* st/glsl: make sure to propagate initialisers to driver storageTimothy Arceri2019-06-045-27/+23
| | | | | | | | | | | | | This essentially reverts 20234cfe3a20. Fixes piglit test: tests/spec/arb_get_program_binary/execution/uniform-after-restore.shader_test Fixes: 20234cfe3a20 "st/mesa: don't propagate uniforms when restoring from cache" Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110784 (cherry picked from commit fea36a8f43ea010ce0581a63b4b5fa1213a35982)
* u_blitter: don't fail mipmap generation for depth formats containing stencilMarek Olšák2019-06-041-1/+2
| | | | | | | | Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=109754 Cc: 19.0 19.1 <mesa-stable@lists.freedesktop.org> Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (cherry picked from commit 4b11ed443b85e4fcddc5d0ef60dec096ecdb951e)
* freedreno/a6xx: fix GPU crash on small render targetsRob Clark2019-06-041-0/+7
| | | | | | | | Fixes dEQP-GLES2.functional.multisampled_render_to_texture.readpixels Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 8eaa2d502131bdce874603f522eabc4a5719f2e6)
* freedreno/ir3: set more barrier bitsRob Clark2019-06-041-0/+1
| | | | | | | | | | | | Blob is also setting the .l bit, and it seems to solve some intermittent failures with a couple of deqp's: dEQP-GLES31.functional.image_load_store.2d.qualifiers.coherent_r32i dEQP-GLES31.functional.image_load_store.2d.qualifiers.volatile_r32f Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Eric Anholt <eric@anholt.net> (cherry picked from commit f9fa456e1d09f1a6b2dccde056b3754f3f198ba7)
* freedreno/ir3: dynamic UBO indexing vs 64b pointersRob Clark2019-06-041-2/+2
| | | | | | | | Fixes dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_fragment and similar things with multiple UBOs Signed-off-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit 6e781a01b97639057d44ca13c5d4276220745b3d)
* nir: Actually propagate progress in nir_opt_move_load_ubo.Bas Nieuwenhuizen2019-05-311-1/+1
| | | | | | | | | | Found with Jasons new metadata rework (https://gitlab.freedesktop.org/mesa/mesa/merge_requests/950). Fixes: af355aaa071 "nir: add nir_opt_move_load_ubo() optimization pass" Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit e24a7840f60ac2290761ea2dc2831e8c3ba8bbfc)
* swr/rast: fix 32-bit compilation on LinuxJan Zielinski2019-05-311-65/+0
| | | | | | | | Removing unused but problematic code from simdlib header to fix compilation problem on 32-bit Linux. Reviewed-by: Alok Hota <alok.hota@intel.com> (cherry picked from commit cf673747cefca03c2b672db6788c1ac2af6d9f33)
* cherry-ignore: add another 19.1 only patchDylan Baker2019-05-301-0/+1
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* cherry-ignore: Add a commit that was manually backportedDylan Baker2019-05-281-0/+4
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* radv: allocate more space in the CS when emitting eventsSamuel Pitoiset2019-05-281-1/+1
| | | | | | | | | | | | If the driver waits for CP DMA to be idle and emit an EOP event we need more space. This fixes a crash with Quake Champions. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 47a10edefb3510d1cae071037dac78a46b31949b)
* Revert "st/mesa: expose 0 shader binary formats for compat profiles for Qt"Timothy Arceri2019-05-284-14/+6
| | | | | | | | | | | This reverts commit 55376cb31e2f495a4d872b4ffce2135c3365b873. It's been over a year and both QT 5.9.5 and 5.11.0 contained a fix for the original issue. It seems i965 only ever applied this workaround to the 18.0 branch. Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 11e16ca7ce0a702088b35ccccea85e243d801ef9)
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