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* VERSION: bump for 22.2.0-rc1mesa-22.2.0-rc1Dylan Baker2022-08-031-1/+1
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* VERSION: bump 22.3.0-devel22.2-branchpointDylan Baker2022-08-031-1/+1
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17875>
* turnip: Use the GMEM CCU space for attachments when the stores won't.Emma Anholt2022-08-031-4/+5
| | | | | | | | | | | | | Since the CCU only gets used for unaligned attachment stores or resolves with the wrong formats, we can use that space for attachments in many cases. This gets two more of vk-5-normal's main renderpass's attachments to fit in the next gmem_pixels increment, leaving 1 to go. Other renderpasses do get better gmem_pixels, and a few get better tile sizes as a result, but the fps increase from those looks to be <.2% at least. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
* turnip: Split the tiling config into separate layouts based on CCU usage.Emma Anholt2022-08-036-253/+369
| | | | | | | | | | | | We now choose between two (equal as of this commit) layouts based on whether the renderpass's stores will use the CCU space, and assert that we always know the chosen layout when we go using the gmem offsets. This required making vkCmdClearAttachments in a secondary take the 3D path instead of gmem blits, since secondaries only have to be compatible with the primary's renderpass, rather than equal. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
* ci/freedreno: Update a630 s8 resolve xfails.Emma Anholt2022-08-031-4/+2
| | | | | | | | | | These tests are all only run in a full vk run. These removed ones were fixed in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17684 and I'm betting the bypass ones were pre-existing (we hadn't updated 630's full vk run list for these new stencil tests, I belive -- my previous full run update was just from one of the two jobs). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
* tu: Restore formatting of tu_clear_blit.cConnor Abbott2022-08-031-1164/+1164
| | | | | | | | Conflict resolution appears to have gone awry. Use my previous resolution of that rebase instead. Fixes: 89263fde2057 ("tu: Use common vk_image struct") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16921>
* iris: Dedent enum iris_depth_reg_modeNanley Chery2022-08-031-5/+5
| | | | | Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
* iris: Make the D16 reg mode single-sampledNanley Chery2022-08-031-7/+9
| | | | | | | | | | | | | | | Wa_14010455700 is dependent on the format and sample count, but our code to track whether or not it had been applied was only dependent on the format. As a result, we failed to enable the workaround when an app used a D16 2xMSAA buffer, then a D16 1xMSAA buffer right afterwards. Make the workaround tracking code sample-dependent to fix this. Cc: mesa-stable Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
* anv: Make the D16 reg mode single-sampledNanley Chery2022-08-032-7/+9
| | | | | | | | | | | | | | | Wa_14010455700 is dependent on the format and sample count, but our code to track whether or not it had been applied was only dependent on the format. As a result, we failed to enable the workaround when an app used a D16 2xMSAA buffer, then a D16 1xMSAA buffer right afterwards. Make the workaround tracking code sample-dependent to fix this. Cc: mesa-stable Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
* nir/lower_idiv: Be less creative about signsAlyssa Rosenzweig2022-08-031-10/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I'm sorry to whoever wrote this, but (x - (int) (x < 0)) ^ -((int) (x < 0)) is not an acceptable way to write iabs. Shader-db results on Intel Tiger Lake with lower_idiv enabled: total instructions in shared programs: 21122548 -> 21122570 (<.01%) instructions in affected programs: 2369 -> 2391 (0.93%) helped: 2 HURT: 8 total cycles in shared programs: 791609360 -> 791608062 (<.01%) cycles in affected programs: 114106 -> 112808 (-1.14%) helped: 9 HURT: 1 If we make the Intel back-end less stupid, we get to 9/1 helped/HURT for instructions as well but that's for a different MR. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17845>
* zink: combine loops for lazy descriptor program deinitMike Blumenkrantz2022-08-031-2/+0
| | | | | | | | | | the bindless and push sets don't have update templates stored to the program, so merging these loops avoids trying to destroy them cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17866>
* zink: don't flag lazy push constant set dirty on batch changeMike Blumenkrantz2022-08-031-2/+2
| | | | | | | | | this has its own flag cc: mesa-stable Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17866>
* zink: fix gfx program cache pruning with generated tcsMike Blumenkrantz2022-08-032-1/+9
| | | | | | | | | | | if the tcs was generated, then the prgram was added to the non-tcs cache, which means deleting it from the tcs+tes cache will fail and then context_destroy will explode Fixes: 4123ee3c714 ("zink: invoke descriptor_program_deinit for programs on context destroy") Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17866>
* ir3: Never remove GS_HEADER_IR3 sysval inputDanylo Piliaiev2022-08-032-12/+13
| | | | | | | | | | | | | | Without GS header geometry shader is never invoked which may cause issues if it has side-effects. Fixes GL CTS tests running via Zink: KHR-GL46.shader_image_load_store.multiple-uniforms KHR-GL46.texture_cube_map_array.image_op_geometry_sh Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6940 Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17771>
* ir3/ra: Always insert interval for precolored inputsDanylo Piliaiev2022-08-031-1/+6
| | | | | | | | | | insert_dst checked whether dst is unused, however for precolored inputs we always want to reserve a reg for them. Input could be unused only if we explicitly want it. Suggested-by: Connor Abbott <cwabbott0@gmail.com> Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17771>
* radeonsi: move small prim precision computation out of si_emit_cull_stateMarek Olšák2022-08-032-24/+22
| | | | | | | | to put it next to its only use and remove the structure fields Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: move the no-AA small prim precision cull constant into an SGPRMarek Olšák2022-08-034-9/+17
| | | | | | | | This reduces the scalar load from vec4 to vec2. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: add a randomized blit testMarek Olšák2022-08-034-21/+586
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: allow texture_map to upload only 1 sample for MSAA instead of allMarek Olšák2022-08-031-8/+19
| | | | | | | | | Reuse the level parameter to do that, which allows us to keep the pipe_transfer size unchanged. It's kinda hacky, but it's the simplest way to do it. This will be used by the blit test to initialize MSAA textures. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: make various blit functions non-staticMarek Olšák2022-08-032-1/+14
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi/gfx11: use a better workaround for the export conflict bugMarek Olšák2022-08-034-3/+17
| | | | | | | This is recommended for better performance. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi/gfx11: enable shader prefetch except for initial chip revisionsMarek Olšák2022-08-033-2/+8
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi/gfx11: rename si_calc_inst_pref_size -> si_get_shader_prefetch_sizeMarek Olšák2022-08-033-6/+6
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi/gfx11: skip code in si_update_shaders that has no effectMarek Olšák2022-08-031-4/+6
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi/gfx11: use better PRIM_GRP_SIZE_GFX11 settingMarek Olšák2022-08-032-4/+8
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi/gfx11: set SAMPLE_MASK_TRACKER_WATERMARK = 15 and clean upMarek Olšák2022-08-032-10/+2
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi/gfx11: use correct VGT_TESS_DISTRIBUTION settingsMarek Olšák2022-08-031-1/+8
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: cosmetic changes around do_hardware_msaa_resolveMarek Olšák2022-08-031-6/+12
| | | | | | | | | | - move gfx_level checking into the function - rename the function - call it in si_blit later - set the SQTT event Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: fold async_copy into the preceding conditional in si_blitMarek Olšák2022-08-031-26/+25
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: move compute-related code from si_blit.c to si_compute_blit.cMarek Olšák2022-08-033-66/+68
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: check for 16-bit hw support instead of relying on options.fp16Marek Olšák2022-08-032-10/+10
| | | | | | | | | options.fp16 can be true even when the hw doesn't support FP16. options.fp16 should only affect the CAP because 16-bit ops can still be used by internal shaders. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: add need_fmask_expand parameter into si_decompress_subresourceMarek Olšák2022-08-033-7/+13
| | | | | | | This is required by MSAA image stores for internal compute blits. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: follow shader_info.float_controls_execution_mode (mostly)Marek Olšák2022-08-0311-20/+58
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: don't do image stores with RGBX, L, LA, I, and SRGB formatsMarek Olšák2022-08-031-0/+8
| | | | | | | | The only change in behavior is that RGBX stores now overwrite X, which is what CB does and it's faster. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: remove compute-based DCC decompression because it's brokenMarek Olšák2022-08-035-156/+37
| | | | | | | The new blit test discovered that it doesn't always work. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: add common helper si_launch_grid_internal_images that is more robustMarek Olšák2022-08-031-54/+57
| | | | | | | It does things in the correct order, which isn't easy to get right. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: make si_launch_grid_internal staticMarek Olšák2022-08-032-4/+2
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: call pipe->blit instead of util_blitter_blit after MSAA resolvingMarek Olšák2022-08-031-3/+1
| | | | | | | | | | | | | This fixes a problem where the destination has a DCC-incompatible view format and triggers a DCC decompression using a custom u_blitter path, which is disallowed inside u_blitter due to it being a u_blitter recursion that always crashes. This is also better because we'll get the best codepath (u_blitter or compute) instead of just u_blitter, Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: move SI_MAX_VRAM_MAP_SIZE to si_debug_options.hMarek Olšák2022-08-033-10/+4
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* radeonsi: unify VGT_TESS_DISTRIBUTION programmingMarek Olšák2022-08-031-12/+19
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* ac/surface: don't forbid 256KB swizzle modes on smaller gfx11 chipsMarek Olšák2022-08-031-7/+1
| | | | | | | let addrlib make the right choice Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* amd/addrlib: fix 3D texture allocation failures on gfx11Marek Olšák2022-08-031-2/+2
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* util/format: add util_format_rgbx_to_rgba helperMarek Olšák2022-08-032-0/+97
| | | | | | | Image stores don't like RGBX on AMD. This is required by compute blits. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
* glthread: don't sync on IsEnabled(GL_DEPTH_TEST) by tracking it in glthreadMarek Olšák2022-08-032-0/+16
| | | | | | | Discovered with viewperf. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17781>
* glthread: don't ignore glPushAttrib/glPopAttrib when tracking GL_CULL_FACEMarek Olšák2022-08-032-0/+7
| | | | | | | Fixes: f4348ef60d51b07 - glthread: don't sync for glIsEnabled with a few enums Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17781>
* r600: increase possible stack size in binary codeGert Wollny2022-08-031-1/+1
| | | | | | | | | | | | | With the trace posted in #6969 we get a nesting level of 149, so make it a round 256 of stack entries. Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6969 Fixes: a4840e15ab77b44a72cabd7d503172e8357477eb r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled. Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17849>
* freedreno/registers/a6xx: Some reg64 conversionRob Clark2022-08-023-69/+50
| | | | | | | Reduce the spurious delta from a7xx regs. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
* freedreno/registers: Move varset to <enum>Rob Clark2022-08-021-128/+128
| | | | | | | De-noisify the enum values that are generation specific. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
* freedreno/registers: Allow varset to be specified on enumRob Clark2022-08-021-0/+1
| | | | | | | | | It gets a bit repetitive to specify the same varset on each value. The rnn decode already handles it when specified on the enum, we just need to relax the schema to allow this. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
* freedreno/registers: Whitespace fix for gen_header.pyRob Clark2022-08-021-1/+1
| | | | | Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17817>
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