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* docs: add release notes for 17.2.6mesa-17.2.6Andres Gomez2017-11-261-0/+188
| | | | Signed-off-by: Andres Gomez <agomez@igalia.com>
* Update version to 17.2.6Andres Gomez2017-11-261-1/+1
| | | | Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: Revert "intel/fs: Use a pure vertical stride for large ↵Andres Gomez2017-11-221-0/+4
| | | | | | | | | register strides" extra: The commit just references a proper fix that has already landed. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functionsAndres Gomez2017-11-221-0/+4
| | | | | | | fixes: This commit makes reference to 2 other commits but none have made it to the 17.2 queue. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: glsl: Fix typo fragement -> fragmentAndres Gomez2017-11-221-0/+3
| | | | | | fixes: This commit is only a typo correction on an error message. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: added 17.3 nominations.Andres Gomez2017-11-221-2/+7
| | | | | | stable: 17.3 nominations only. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: i965: Mark BOs as external when we export their handleAndres Gomez2017-11-221-0/+5
| | | | | | | stable: These commits addressed earlier commit 2c4097aff1b which did not land in branch. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: anv/cmd_buffer: Take bo_offset into account in fast clear ↵Andres Gomez2017-11-221-0/+4
| | | | | | | | | state addresses stable: This commit addressed earlier commit a62a97933578 which did not land in branch. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: anv/cmd_buffer: Advance the address when initializing clear ↵Andres Gomez2017-11-221-0/+4
| | | | | | | | | colors stable: This commit depends on earlier commit 3735af04152b which did not land in branch. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: r600/shader: reserve first register of vertex shader.Andres Gomez2017-11-221-0/+4
| | | | | | | stable: This commit addressed earlier commit ea1b97714d9b which did not land in branch. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: intel/fs: refactorsAndres Gomez2017-11-221-0/+5
| | | | | | stable: These commits are refactorings rather than fixes. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: intel/fs: Use the original destination region for int MUL ↵Andres Gomez2017-11-221-0/+4
| | | | | | | | | lowering stable: These commits resulted in a CTS regression being addressed at https://bugs.freedesktop.org/show_bug.cgi?id=103626 . Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: intel/nir: Use the correct indirect lowering masks in ↵Andres Gomez2017-11-221-0/+6
| | | | | | | | | link_shaders stable: These commits addressed earlier commit 379b24a40d3 which did not land in branch. Signed-off-by: Andres Gomez <agomez@igalia.com>
* cherry-ignore: intel/fs: Use a pure vertical stride for large register stridesAndres Gomez2017-11-221-0/+3
| | | | | | stable: This commit is not really needed after 6ac2d169019. Signed-off-by: Andres Gomez <agomez@igalia.com>
* ddebug: fix use-after-free of streamout targetsNicolai Hähnle2017-11-221-1/+1
| | | | | | Fixes: b47727a83ad6 ("ddebug: implement pipelined hang detection mode") Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 16f8da299700e714fd5aff265b8f28fe2badfa95)
* glsl: Catch subscripted calls to undeclared subroutinesGeorge Barrett2017-11-221-2/+7
| | | | | | | | | | | generate_array_index fails to check whether the target of a subroutine call exists in the AST, potentially passing around null ir_rvalue pointers eventuating in abort/segfault. Fixes: fd01840c0bd3 ("glsl: add AoA support to subroutines") Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100438 (cherry picked from commit f09c2cefdd53cd61562a994294e9d0630868d2da)
* i965: Upload invariant state once at the start of the batch on Gen4-5.Kenneth Graunke2017-11-224-13/+3
| | | | | | | | | | | | | | | | | | | | | | | | | We want to emit invariant state at the start of a render batch. In the past, this more or less happened: a new batch flagged BRW_NEW_CONTEXT (because we don't have hardware contexts), which triggered the brw_invariant_state atom. So, it would be emitted before any 3D drawing. (Technically, there might be some BLT commands in the batch because Gen4-5 have a single combined render/BLT ring, but that should be harmless). With the advent of BLORP, this broke. The first item in a batch might be a BLORP operation, which bypasses the normal draw upload path. So, we need to ensure invariant state happens first. To do that, we just upload it when creating a new batch. On Gen6+ we'd need to worry about whether it's a RENDER or BLT batch, but because we have a combined ring, this approach should work fine on Gen4-5. Seems to fix GPU hangs when playing hardware accelerated video with mpv -hwdec=vaapi on Ironlake. Cc: mesa-stable@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103529 Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 8f91aa35a54e127b68415376ef2b577ea8fc30f9)
* egl/wayland: Add a fallback when fourcc query isn't supportedDerek Foreman2017-11-221-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When queryImage doesn't support __DRI_IMAGE_ATTRIB_FOURCC wayland clients will die with a NULL derefence in wl_proxy_add_listener. Attempt to provide a simple fallback to keep ancient systems working. Fixes: 6595c699511 ("egl/wayland: Remove more surface specifics from create_wl_buffer") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103519 Signed-off-by: Derek Foreman <derekf@osg.samsung.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Acked-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (cherry picked from commit 0db36caa192b129cb4f22d152f82f38fcf6f06d4) Squashed with: egl: fix var type queryImage() takes an `int*`; compiler is warning about the signed<->unsigned pointer mismatch. Fixes: 0db36caa192b129cb4f2 "egl/wayland: Add a fallback when fourcc query isn't supported" Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Frank Binns <frank.binns@imgtec.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Derek Foreman <derekf@osg.samsung.com> (cherry picked from commit ca95d7ad4e1b900eb3d559ed5bda0b96b232961d)
* i965: Implement another VF cache invalidate workaround on Gen8+.Kenneth Graunke2017-11-221-8/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ...and provide a better citation for the existing one. v2: - Apply the workaround to Gen8 too, as intended (caught by Topi). - Restructure to add bits instead of an extra flush (based on a similar patch by Rafael Antognolli). Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> (cherry picked from commit 8d48671492412e04c18651a779cabacf30ed0afe) [Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen] Signed-off-by: Andres Gomez <agomez@igalia.com> Conflicts: src/mesa/drivers/dri/i965/brw_pipe_control.c Squashed with: i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround. This apparently causes hangs on Broadwell, so let's back it out for now. I think there are other PIPE_CONTROL workarounds that we're missing. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787 (cherry picked from commit a01ba366e01b7d1cdfa6b0e6647536b10c0667ef) [Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen] Signed-off-by: Andres Gomez <agomez@igalia.com> Conflicts: src/mesa/drivers/dri/i965/brw_pipe_control.c
* i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLKMatt Turner2017-11-211-4/+4
| | | | | | | | | Fixes the following tests on CHV, BXT, and GLK: KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115 (cherry picked from commit cfcfa0b9cd1b1d563a988b1250950057c4612ac9)
* i965/fs: Fix extract_i8/u8 to a 64-bit destinationMatt Turner2017-11-211-2/+23
| | | | | | | | | | | | | | | | | The MOV instruction can extract bytes to words/double words, and words/double words to quadwords, but not byte to quadwords. For unsigned byte to quadword, we can read them as words and AND off the high byte and extract to quadword in one instruction. For signed bytes, we need to first sign extend to word and the sign extend that word to a quadword. Fixes the following test on CHV, BXT, and GLK: KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628 Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 6ac2d16901927013393f873a34c717ece5014c1a)
* i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DWAnuj Phogat2017-11-212-4/+17
| | | | | | | | | | | | | | Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Cc: <mesa-stable@lists.freedesktop.org> (cherry picked from commit 1dc45d75bb3ff3085f7356b8ec658111529ff76d) [Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen] Signed-off-by: Andres Gomez <agomez@igalia.com> Conflicts: src/mesa/drivers/dri/i965/brw_pipe_control.c src/mesa/drivers/dri/i965/intel_blit.c
* i965: Program DWord Length in MI_FLUSH_DWAnuj Phogat2017-11-213-3/+3
| | | | | | | | | | | | | | | | | Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Cc: <mesa-stable@lists.freedesktop.org> (cherry picked from commit 6165fda59b889de035b38d9a1a08ffe0da19e6a6) Squashed with: i965: Remove DWord length from MI_FLUSH_DW definition Fixes: 6165fda59b8 ("i965: Program DWord Length in MI_FLUSH_DW") Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 822fd2341db49cbbe813114d2d0fc1b66de4807c)
* swr/rast: Faster emulated simd16 permuteTim Rowley2017-11-211-23/+11
| | | | | | | | | Speed up simd16 frontend (default) on avx/avx2 platforms; fixes performance regression caused by switch to simdlib. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit d8489517a572c7e5c5405ebf510db9d20b1e2591)
* swr/rast: Use gather instruction for i32gather_ps on simd16/avx512Tim Rowley2017-11-211-11/+1
| | | | | | | | | Speed up avx512 platforms; fixes performance regression caused by swithc to simdlib. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 439904847e9c2970494c18e8c47bd6c38c0ed8ab)
* radv: Free temporary syncobj after waiting on it.Bas Nieuwenhuizen2017-11-211-4/+18
| | | | | | | | Otherwise we leak it. Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)" Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 7c255788637b8fdfc31aca5f7891f39a110c5cb2)
* radv: Free syncobj with multiple imports.Bas Nieuwenhuizen2017-11-211-2/+8
| | | | | | | | | Otherwise we can leak the old syncobj. Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)" Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 917d3b43f2b206ccf036542aa1c39f1dbdd84f62)
* i965: Add stencil buffers to cache set regardless of stencil texturingJason Ekstrand2017-11-211-3/+1
| | | | | | | | | We may access them as a texture using blorp regardless of whether or not stencil texturing is enabled. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 6830ba0d3be8df12572622839743c41b4f294825)
* r600: fix isoline tess factor component swapping.Dave Airlie2017-11-211-0/+7
| | | | | | | | | | As per radeonsi, the tess factor components for isolines are reversed. Fixes: tests/spec/arb_tessellation_shader/execution/isoline.shader_test Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit f3f8615d76b20ad66466b172a600e06b9a833729)
* intel/tools: Fix detection of enabled shader stages.Kenneth Graunke2017-11-211-1/+1
| | | | | | | | | | | We renamed "Function Enable" to "Enable", which broke our detection of whether shaders are enabled or not. So, we'd see a bunch of HS/DS packets with program offsets of 0, and think that was a valid TCS/TES. Fixes: c032cae9ff77e (genxml: Rename "Function Enable" to "Enable".) Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 9a0465b3a3a1a6e8beda7a59506c2e1a1aae776f)
* i965: Make L3 configuration atom listen for TCS/TES program updates.Kenneth Graunke2017-11-211-0/+2
| | | | | | | | | | | The L3 configuration code already considers the TCS and TES programs, but failed to listen for TCS/TES program changes. This was somehow missing. Fixes: e9644cb1f96ccf7e ("i965: Consider tessellation in get_pipeline_state_l3_weights.") Reviewed-by: Francisco Jerez <currojerez@riseup.net> (cherry picked from commit b8d42cccd053e32ca048645ea7e6f901366e286d)
* autotools: Set C++ visibility flags on IntelDylan Baker2017-11-211-0/+3
| | | | | | | | | | These flags are set for C sources, but not C++. This causes symbol visibility leaks from the C++ parts of the Intel compiler. Fixes: 700bebb958e93f4d ("i965: Move the back-end compiler to src/intel/compiler") Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 854455498c0370e959c0bb25680641e05faea3e2)
* glx/dri3: Fix passing renderType into glXCreateContextAdam Jackson2017-11-211-1/+2
| | | | | | | | | | | Without this, trying to create a GLX_RGBA_FLOAT_TYPE_ARB context would fail, because GLX_RGBA_TYPE would be a mismatch with the fbconfig. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Adam Jackson <ajax@redhat.com> (cherry picked from commit 257edb5b9aedc9fc5d5c13eb2f48a0c11d15456f)
* glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)Adam Jackson2017-11-211-4/+2
| | | | | | | | | | | | This is perfectly legal in GL 3.0+. Fixes piglit/glx-create-context-current-no-framebuffer. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Adam Jackson <ajax@redhat.com> (cherry picked from commit 033cfb17db85b38bc012d74f30f6c92cddf85216)
* nir/spirv: tg4 requires a samplerAlex Smith2017-11-212-2/+1
| | | | | | | | | | | Gather operations in both GLSL and SPIR-V require a sampler. Fixes gathers returning garbage when using separate texture/samplers (on AMD, was using an invalid sampler descriptor). Signed-off-by: Alex Smith <asmith@feralinteractive.com> Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 4122d008466cef47eaa3f958924618060f4e4330)
* spirv: Use correct type for sampled imagesAlex Smith2017-11-213-6/+6
| | | | | | | | | | | | | | | | | | | | | | | We should use the result type of the OpSampledImage opcode, rather than the type of the underlying image/samplers. This resolves an issue when using separate images and shadow samplers with glslang. Example: layout (...) uniform samplerShadow s0; layout (...) uniform texture2D res0; ... float result = textureLod(sampler2DShadow(res0, s0), uv, 0); For this, for the combined OpSampledImage, the type of the base image was being used (which does not have the Depth flag set, whereas the result type does), therefore it was not being recognised as a shadow sampler. This led to the wrong LLVM intrinsics being emitted by RADV. Signed-off-by: Alex Smith <asmith@feralinteractive.com> Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit e9eb3c4753e4f56b03d16d8d6f71d49f1e7b97db)
* configure.ac: require xcb* for the omx/va/... when using x11 platformEmil Velikov2017-11-211-1/+3
| | | | | | | | | | | | | Targets such as omx and va can work w/o anything X related. Mandate the xcb* dependencies only when the X11 platform is selected. Reported-by: Lukas Rusak <lorusak@gmail.com> Fixes: 63e11ac2b5c ("configure: error out if building VA w/o supported platform") Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Tested-by: Lukas Rusak <lorusak@gmail.com> (v1) (cherry picked from commit 85a017230cacd0661570421c8e5b0619e512d33d)
* configure.ac: loosen --enable-glvnd check to honour eglEmil Velikov2017-11-211-8/+4
| | | | | | | | | | | | | | | | Currently we error out when building GLVND w/o GLX. That was the original premice before we had EGL. As the commit says, that error should be reworked to honour both - do so. v2: Drop noop *);; (Eric) Reported-by: Lukas Rusak <lorusak@gmail.com> Fixes: ce562f9e3fa ("EGL: Implement the libglvnd interface for EGL (v3)") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Tested-by: Lukas Rusak <lorusak@gmail.com> (v1) (cherry picked from commit b4967561c035182b64d3ae0f474d4ef281535ce1)
* glsl: Transform fb buffers are only active if a variable uses themNeil Roberts2017-11-211-9/+15
| | | | | | | | | | | | | | | | The GL spec will soon be revised to clarify that a buffer binding for a transform feedback buffer is only required if a variable is actually defined to use the buffer binding point. Previously a declaration for the default transform buffer would make it require a binding even if nothing was declared to use the default buffer. Affects: KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list_and_api Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 4dc8458cd13154daa48bd97c3f8393daf02aa351)
* mesa: rework how we free gl_shader_program_dataTimothy Arceri2017-11-213-42/+18
| | | | | | | | | | | | | | | | | When I introduced gl_shader_program_data one of the intentions was to fix a bug where a failed linking attempt freed data required by a currently active program. However I seem to have failed to finish hooking up the final steps required to have the data hang around. Here we create a fresh instance of gl_shader_program_data every time we link. gl_program has a reference to gl_shader_program_data so it will be freed once the program is no longer active. Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Neil Roberts <nroberts@igalia.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102177 (cherry picked from commit 6a72eba755fea15a0d97abb913a6315d9d32e274)
* glsl: use the correct parent when allocating program data membersTimothy Arceri2017-11-214-8/+8
| | | | | | | Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 9c33533586476693a197b7179552d140d54f23f2)
* glsl: drop cache_fallbackTimothy Arceri2017-11-215-77/+55
| | | | | | | | | | | This turned out to be a dead end, it is much easier and less error prone to just cache the IR used by the drivers backend e.g. TGSI or NIR. Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit cf05bb506a075c9e3b8a3c374b928ff0367c49b2)
* i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTEKenneth Graunke2017-11-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This has a bit of a surprising effect: For the render pipeline, the upload_sampler_state_table atom emits 3DSTATE_BINDING_TABLE_POINTERS_XS. It tries to avoid this for compute: if (GEN_GEN >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) { /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */ genX(emit_sampler_state_pointers_xs)(brw, stage_state); } ... However, we were failing to initialize brw->cs.base.stage, so it was left as 0 (MESA_SHADER_VERTEX), causing this condition to break. We then emitted 3DSTATE_SAMPLER_STATE_POINTERS_VS in GPGPU mode, when trying to upload CS samplers. Nothing good can come of this. Found by inspection while debugging a GPU hang. Jordan believes this helps the Deus Ex: Mankind Divided benchmark mode's stability when running with shader cache. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (cherry picked from commit a16dc04ad51c32e5c7d136e4dd6273d983385d3f) [Andres Gomez: resolve trivial conflicts] Signed-off-by: Andres Gomez <agomez@igalia.com> Conflicts: src/mesa/drivers/dri/i965/brw_context.c
* targets/opencl: don't hardcode the icd file install to /etc/...Emil Velikov2017-11-211-1/+1
| | | | | | | | | | | | | | | | | Use $(sysconfdir) instead of hardcoding /etc. While the OpenCL spec expects the file in /etc, people building their stack can override that, esp. !Linux users. Furthermore this removes a fundamental violation, which results in the system file being overwritten even as one explicitly sets --prefix and/or DESTDIR. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-By: Aaron Watry <awatry@gmail.com> (cherry picked from commit 0cd09585441d15ef1ff49de497008103f0b0e1ac)
* intel/fs: Rework zero-length URB write handlingJason Ekstrand2017-11-211-29/+31
| | | | | | | | | | | | | | | Originally we tried to handle this case based on slots_valid. However, there are a number of ways that this can go wrong. For one, we throw away any trailing slots which either aren't written or are set to VARYING_SLOT_PAD. Second, even if PSIZ is a valid slot, we may not actually write anything there. Between the lot of these, it was possible to end up in a case where we tried to do a regular URB write but ended up with a length of 1 which is invalid. This commit moves it to the end and makes it based on a new boolean flag urb_written. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 7a82ad54bb56cafaeea7f909cd9fc35542c23ba0)
* intel/fs: Mark 64-bit values as being contiguousJason Ekstrand2017-11-211-1/+4
| | | | | | | | | | | | This isn't often a problem , when we're in a compute shader, we must push the thread local ID so we decrement the amount of available push space by 1 and it's no longer even and 64-bit data can, in theory, span it. By marking those uniforms contiguous, we ensure that they never get split in half between push and pull constants. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 25f7453c9e6dc7c947b936bdac86680c332362bf)
* intel/fs: Fix integer multiplication lowering for src/dst hazardsJason Ekstrand2017-11-211-2/+8
| | | | | | Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit d54f8ec744545673fd78f15ffce3cb4e47d4b5f1)
* intel/fs: Fix MOV_INDIRECT for 64-bit values on little-coreJason Ekstrand2017-11-211-36/+39
| | | | | | | | | | The same workaround we need for 64-bit values on little core also takes care of the Ivy Bridge problem and does so a bit more efficiently so we can drop that code while we're here. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit fd1bcccc2de9ba6a1ad6171342a155091963c3b9)
* intel/eu/reg: Add a subscript() helperJason Ekstrand2017-11-211-0/+16
| | | | | | | | This is similar to the identically named fs_reg helper. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 10e4feed39120072f38274b95e884422f72f360f)
* intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/allJason Ekstrand2017-11-211-9/+33
| | | | | | | | | | | | For some reason, the any/all predicates don't work properly with SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H doesn't read the correct subset of the flag register and you end up getting garbage in the second half. Work around this by using a pair of 1-wide MOVs and scattering the result. This fixes the any/all instructions for SIMD32. Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 1b8ef49f48ae3634e4903422a9d9c11864c03cb1)
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