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* android: radeonsi: fix build after vl refactoring (v2)android-radeonsi-build-fixMauro Rossi2019-12-043-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | vl functions moved from radeonsi to gallium/auxiliary/vl have left android build of radeonsi in broken state. libmesa_galliumvl static is need to build readeonsi, gallium_dri building rules are reworked to avoid multiple symbols and libmesa_galliumvl static dependency is needed in radeonsi. Here is the changelog: - android: gallium/auxiliary: add libmesa_galliumvl static - android: gallium_dri: move libmesa_gallium to static to prevent multiple symbols - android: radeonsi: fix build after vl refactoring Fixes the following building error: external/mesa/src/gallium/drivers/radeonsi/si_uvd.c:47: error: undefined reference to 'vl_video_buffer_create_as_resource' clang.real: error: linker command failed with exit code 1 (use -v to see invocation) Fixes: 86e60bc ("radeonsi: remove si_vid_join_surfaces and use combined planar allocations") Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* docs: Update mesa 19.3 release calendarDylan Baker2019-12-041-15/+3
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* docs: update calendar, add news item and link release notes for 19.2.7Dylan Baker2019-12-043-9/+3
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* docs: Add SHA256 sums for 19.2.7Dylan Baker2019-12-041-1/+1
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* docs: Add release notes for 19.2.7Dylan Baker2019-12-041-0/+96
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* turnip: allow writes to draw_cs outside of render passJonathan Marek2019-12-041-4/+3
| | | | | | | | | This is for state commands like CmdSetViewport that can be used outside of a renderpass. Accumulating those into draw_cs outside of the renderpass should have the desired effect. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net>
* nir/lower_clip: Fix incorrect driver loc for clipdist outputsRob Clark2019-12-041-0/+11
| | | | | | | | | | | Somehow adjusting maxloc based on existing outputs got lost, resulting in the clipdist varying clobbering the position varying. Causing a shader that had no position output in freedreno/ir3, which triggers GPU hangs in neverball. Fixes: d0f746b6458 ("nir: Save nir_variable pointers in nir_lower_clip_vs rather than locs.") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* freedreno/ir3: fix neverball assert in case of unused VS inputsRob Clark2019-12-043-7/+19
| | | | | | | | | | | | | | | The logic to ensure VS and BS inputs are aligned wasn't accounting for unused inputs in VS. This *usually* doesn't happen, but it seems it can in the case of ARB programs? Fixes assert: ``` fd6_program_create: Assertion `bs->inputs[i].regid == vs->inputs[i].regid' failed. ``` Fixes: 882d53d8e36 ("freedreno/ir3+a6xx: same VBO state for draw/binning") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* freedreno/ir3: remove store_output lowered to store_shared_ir3Rob Clark2019-12-041-1/+1
| | | | | | | | | | | | | | | Fixes crashes that were unnoticed in CI because debug_assert() was not enabled (but become real crashes after the next patch): dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.ivec2_highp_geometry dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.ivec2_lowp_geometry dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.ivec2_mediump_geometry dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.uvec2_highp_geometry dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.uvec2_lowp_geometry dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.uvec2_mediump_geometry Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* iris: Add restriction to 3DSTATE_CONSTANT_ packets.Rafael Antognolli2019-12-041-0/+11
| | | | | | | | | | | | | The following programming note shows up in all 3DSTATE_CONSTANT_* packets: "The sum of all four read length fields must be less than or equal to the size of 64." The backend compiler should guarantee this for us, so let's just add a check here. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* anv: Use 3DSTATE_CONSTANT_ALL when possible.Rafael Antognolli2019-12-041-3/+90
| | | | | | | | | | | | | | | | | | | | | | | | Use this new instruction introduced in Gen12. The instruction itself is smaller, and it also allows us to emit a single instruction to all stages that have the same push constant buffers (e.g. when they don't have constant buffers). There's one restriction to use this instruction, though: the length field is only 5 bits long, so we need to check whether we can use it, and fallback to the old 3DSTATE_CONSTANT_XS if that field is >= 32. v2: - Rebased on top of the lasted changes from Jason. - Added review suggestions by Caio. - Removed struct push_bos and merged some code into anv_nir_compute_push_layout(). v3: - Remove code churn due to gen8+ workaround in anv_nir_compute_push_layout(). This code has been removed in an earlier commit, and implemented in cmd_buffer_emit_push_constant(). Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* anv: Move code for emitting push constants into its own function.Rafael Antognolli2019-12-041-43/+57
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* anv: Add get_push_range_address() helper.Rafael Antognolli2019-12-041-59/+70
| | | | | | | | | | | Add a helper function to get the push range address. Once we have a separate function for emitting gen12 push constants, we can use this helper and avoid duplicating code. v3: Do not add range->start to the address in gen7 (Caio). v4: Do not drop range->start from gen7 (Caio, Jason). Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* anv: Move gen8+ push constant packet workaround.Rafael Antognolli2019-12-042-21/+31
| | | | | | | | | | | | | | | | | | | Store push_ranges in ascending order, and only "shift" them to the end of the array during state packet emission. We don't need this workaround with the new 3DSTATE_CONSTANT_ALL packet. So instead of applying the workaround here just for GEN < 12 (which requires and extra loop through all the ranges to figure out if we should shift them or not), we simply move the whole logic to the state emission code. At that point, in a later commit, we are already looping through all of the ranges anyway to check which packet we will be using, so we might as well implement the workaround there, where it is going to be used. v3: Move gen8+ workaround to the state emission code (Caio). v4: Add explanation of why we moved the workaroudn (Caio). Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* iris: Use 3DSTATE_CONSTANT_ALL when possible.Rafael Antognolli2019-12-042-2/+76
| | | | | | | | | | | | | | | | | | | | Use this new instruction introduced in Gen12. The instruction itself is smaller, and it also allows us to emit a single instruction to all stages that have the same push constant buffers (e.g. when they don't have constant buffers). There's one restriction to use this instruction, though: the length field is only 5 bits long, so we need to check whether we can use it, and fallback to the old 3DSTATE_CONSTANT_XS if that field is >= 32. v2 (Suggestions from Caio): - use max_length instead of large_buffers. - remove UNUSED and use #if GEN_GEN >= 12 instead. - inline "buffers" and drop BITSET_RANGE() usage. - add assert(n <= max_pointers) - move emit to outside of the loop. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* iris: Rework push constants emitting code.Rafael Antognolli2019-12-041-42/+83
| | | | | | | | | | | | | | | | | | | | | Split into a function the logic to gather the push constant buffers, which now stores them in struct push_bos. Another function is added to emit the packet, using data from the push_bos struct. This will be useful when adding a new function for emitting push constants for newer platforms. v2 (Suggestions from Caio): - rename 'n' -> 'buffer_count' - remove large_buffers (for now) - initialize push_bos - remove assert - change for() condition (i <= 3 -> i < 4) v3: - Add comment about size limit. - Rework "shift" logic and 'for' loop. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* intel/blorp: Use 3DSTATE_CONSTANT_ALL to setup push constants.Rafael Antognolli2019-12-041-0/+7
| | | | | | | | | | In blorp, all the push constants are disabled, so we only need to emit a single 3DSTATE_CONSTANT_ALL with the bitmask for stage update appropriately set. v2: Update comment (Caio). Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* intel/aubinator: Decode 3DSTATE_CONSTANT_ALL.Rafael Antognolli2019-12-041-0/+44
| | | | | Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
* intel/genxml: Add 3DSTATE_CONSTANT_ALL packet.Rafael Antognolli2019-12-041-0/+25
| | | | Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
* turnip: MSAA resolve directly from GMEMJonathan Marek2019-12-043-50/+32
| | | | | Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net>
* turnip: don't set unused BLIT_DST_INFO bits for GMEM clearJonathan Marek2019-12-041-7/+1
| | | | | | | | | These bits are ignored when clearing so don't bother setting them. Note: MSAA samples when clearing comes from other registers (tu6_emit_msaa) Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net>
* turnip: implement CmdClearAttachmentsJonathan Marek2019-12-041-1/+65
| | | | | | | Passes these deqp tests: dEQP-VK.api.image_clearing.core.*attach*single* Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net>
* turnip: don't skip unused attachments when setting up tiling configJonathan Marek2019-12-041-18/+10
| | | | | | | This makes it easier to find the gmem_offset associated with an attachment. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net>
* lima: enable tilingVasily Khoruzhick2019-12-041-11/+30
| | | | | | | | | | | Now that we have tiled format modifier merged into linux we can enable tiling. That should improve overall performance and also workaround broken mipmapping for linear textures since now we prefer tiled textures. Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
* glsl: additional interface redeclaration check for SSO programsTapani Pälli2019-12-041-0/+54
| | | | | | | | | | | Patch adds additional linker check for SSO programs to make sure they are redeclaring built-in blocks as required by the desktop spec. This fixes following Piglit tests: arb_separate_shader_objects/linker/pervertex-* Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
* gitlab-ci: bump piglit checkout commitTapani Pälli2019-12-044-8/+25
| | | | | | | | Commit also updates the Piglit quick_gl.txt, list modifications happened due to following Piglit commits: c248bf201,c acff58ca, 5603e2e60. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
* nir/load_store_vectorize: fix combining stores with aliasing loads betweenRhys Perry2019-12-042-2/+16
| | | | | | | | | v2: add test Fixes: ce9205c03bd ('nir: add a load/store vectorization pass') Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v1) Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v2)
* aco/wave32: Fix reductions.Timur Kristóf2019-12-043-30/+45
| | | | | Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco/wave32: Allow setting the subgroup ballot size to 64-bit.Timur Kristóf2019-12-042-4/+8
| | | | | | | | | Previously, it would only work when the ballot size was set to the lane mask. This patch makes is possible to set the ballot size to either 32-bit or 64-bit for wave32 mode. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco/wave32: Use wave_size for barrier intrinsic.Timur Kristóf2019-12-042-3/+3
| | | | | | Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco/wave32: Fix load_local_invocation_index to support wave32.Timur Kristóf2019-12-041-3/+15
| | | | | Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco/wave32: Use lane mask regclass for exec/vcc.Timur Kristóf2019-12-0412-209/+250
| | | | | | | | | Currently all usages of exec and vcc are hardcoded to use s2 regclass. This commit makes it possible to use s1 in wave32 mode and s2 in wave64 mode. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco/wave32: Add wave size specific opcodes to aco_builder.Timur Kristóf2019-12-041-0/+78
| | | | | | | | | | | | | Several places in ACO we use SOP1 or SOP2 instructions to operate over the exec mask or VCC, and these need to be adapted to the new size in wave32 mode. This commit adds a way to deal with this problem in aco_builder: the caller can specify a wave size specific opcode and the builder will translate that to the correct opcode based on the current wave size. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco/wave32: Introduce emit_mbcnt which takes wave size into account.Timur Kristóf2019-12-041-17/+24
| | | | | | | | This is relevant because in wave32 mode the v_mbcnt_hi_u32_b32 instruction is superfluous. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco/wave32: Replace hardcoded numbers in spiller with wave size.Timur Kristóf2019-12-041-15/+16
| | | | | Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco/wave32: Change uniform bool optimization to work with wave32.Timur Kristóf2019-12-041-1/+2
| | | | | | Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco: Optimize load_subgroup_id to one bit field extract instruction.Timur Kristóf2019-12-041-3/+2
| | | | | | Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco: Remove lower_linear_bool_phi, it is not needed anymore.Timur Kristóf2019-12-041-24/+1
| | | | | | Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco: Remove superfluous argument from emit_boolean_logic.Timur Kristóf2019-12-041-6/+6
| | | | | | Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* aco: Fix operand of s_bcnt1_i32_b64 in emit_boolean_reduce.Timur Kristóf2019-12-041-1/+1
| | | | | | Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* gitlab-ci: Run piglit glslparser & quick_shader tests separatelyMichel Dänzer2019-12-044-6512/+5328
| | | | | | | | | | | And only use --process-isolation false for the quick_gl tests. This will hopefully avoid variance in the test results that we've been seeing lately. But even if it doesn't, it should at least help narrow down the cause of the variance. Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
* intel/perf: fix improper pointer accessLionel Landwerlin2019-12-041-1/+1
| | | | | | | | | | This expression was unused by the macro, probably why it didn't register in the compilation. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/perf: simplify the processing of OA reportsLionel Landwerlin2019-12-041-28/+36
| | | | | | | | | | | | | | | | | | | | | | | | This is a more accurate description of what happens in processing the OA reports. Previously we only had a somewhat difficult to parse state machine tracking the context ID. What we really only need to do to decide if the delta between 2 reports (r0 & r1) should be accumulated in the query result is : * whether the r0 is tagged with the context ID relevant to us * if r0 is not tagged with our context ID and r1 is: does r0 have a invalid context id? If not then we're in a case where i915 has resubmitted the same context for execution through the execlist submission port v2: Update comment (Ken) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/perf: take into account that reports read can be fairly oldLionel Landwerlin2019-12-041-3/+4
| | | | | | | | | | | | | | | If we read the OA reports late enough after the query happens, we can get a timestamp in the report that is significantly in the past compared to the start timestamp of the query. The current code must deal with the wraparound of the timestamp value (every ~6 minute). So consider that if the difference is greater than half that wraparound period, we're probably dealing with an old report and make the caller aware it should read more reports when they're available. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/perf: set read buffer len to 0 to identify empty bufferLionel Landwerlin2019-12-041-2/+3
| | | | | | | | | | | | | | | | | We always add an empty buffer in the list when creating the query. Let's set the len appropriately so that we can recognize it when we read OA reports up to the end of a query. We were using an 0 timestamp value associated with the empty buffer and incorrectly assuming this was a valid value. In turn that led to not reading enough reports and resulted in deltas added to our counter values which should have been discarded because those would be flagged for a different context. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel/perf: fix invalid hw_id in query resultsLionel Landwerlin2019-12-041-2/+6
| | | | | | | | | | | | Accumulation happens between 2 reports, it can be between a start/end report from another context. So only consider updating the hw_id of the results when it's not already valid and that we have a valid value to put in there. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 41b54b5faf ("i965: move OA accumulation code to intel/perf") Reviewed-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* radeonsi: display cs blit count for AMD_DEBUG=testdmaPierre-Eric Pelloux-Prayer2019-12-041-3/+5
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: implement sdma for GFX9Pierre-Eric Pelloux-Prayer2019-12-041-6/+191
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radv/gfx10: fix the vertex order for triangle strips emitted by a GSSamuel Pitoiset2019-12-041-48/+47
| | | | | | | | | My fix wasn't totally correct as pointed out by Marek. Ported from RadeonSI. Fixes: deafe4cc587 ("radv/gfx10: fix primitive indices orientation for NGG GS") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* radv: simplify a check in radv_fixup_vertex_input_fetches()Samuel Pitoiset2019-12-041-4/+2
| | | | | | | The number of loaded channels should always be > 0 now. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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