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| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2019-01-17 09:33:36 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2019-01-23 11:31:07 +0100 |
| commit | bd098884f101937de0819200b9cdcaee11aa6f1d (patch) | |
| tree | 71f8e1840a728e1932638e23e7fb28744b222eac /src/amd/vulkan/si_cmd_buffer.c | |
| parent | 698afa177ec52220b3f0045f6488d91e5405ab3d (diff) | |
| download | mesa-bd098884f101937de0819200b9cdcaee11aa6f1d.tar.gz | |
radv: remove old_fence parameter from si_cs_emit_write_event_eop()
This parameter is actually useless as the immediate value
can always be zero.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Diffstat (limited to 'src/amd/vulkan/si_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 2f57584bf82..2f32c72fea1 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -660,7 +660,6 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, unsigned event, unsigned event_flags, unsigned data_sel, uint64_t va, - uint32_t old_fence, uint32_t new_fence, uint64_t gfx9_eop_bug_va) { @@ -707,7 +706,7 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, radeon_emit(cs, op); radeon_emit(cs, va); radeon_emit(cs, ((va >> 32) & 0xffff) | sel); - radeon_emit(cs, old_fence); /* immediate data */ + radeon_emit(cs, 0); /* immediate data */ radeon_emit(cs, 0); /* unused */ } @@ -801,7 +800,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DATA_SEL_DISCARD, - 0, 0, 0, + 0, 0, gfx9_eop_bug_va); } } @@ -868,11 +867,11 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, RADV_CMD_FLAG_INV_VMEM_L1); } assert(flush_cnt); - uint32_t old_fence = (*flush_cnt)++; + (*flush_cnt)++; si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags, EOP_DATA_SEL_VALUE_32BIT, - flush_va, old_fence, *flush_cnt, + flush_va, *flush_cnt, gfx9_eop_bug_va); radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); |