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| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2019-07-16 17:35:00 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2019-07-17 08:32:36 +0200 |
| commit | ed53d2c4be2af281382fcf16091a6ee6739d0da0 (patch) | |
| tree | b8b7aaa2cdbd812eb78af58ee40801a7973f1906 /src/amd/vulkan/radv_image.c | |
| parent | edf1af696f74b4ac4efa4a7f62b33099a36b3a30 (diff) | |
| download | mesa-ed53d2c4be2af281382fcf16091a6ee6739d0da0.tar.gz | |
radv/gfx10: disable the TC compat zrange workaround
Unnecessary.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Diffstat (limited to 'src/amd/vulkan/radv_image.c')
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index ccbec36849e..4d3ed71c23c 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1186,14 +1186,15 @@ radv_image_alloc_dcc(struct radv_image *image) } static void -radv_image_alloc_htile(struct radv_image *image) +radv_image_alloc_htile(struct radv_device *device, struct radv_image *image) { image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment); /* + 8 for storing the clear values */ image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size; image->size = image->clear_value_offset + 8; - if (radv_image_is_tc_compat_htile(image)) { + if (radv_image_is_tc_compat_htile(image) && + device->physical_device->has_tc_compat_zrange_bug) { /* Metadata for the TC-compatible HTILE hardware bug which * have to be fixed by updating ZRANGE_PRECISION when doing * fast depth clears to 0.0f. @@ -1402,7 +1403,7 @@ radv_image_create(VkDevice _device, if (radv_image_can_enable_htile(image) && !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) { image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE; - radv_image_alloc_htile(image); + radv_image_alloc_htile(device, image); } else { radv_image_disable_htile(image); } |