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| author | Sagar Ghuge <sagar.ghuge@intel.com> | 2019-05-21 16:15:16 -0700 |
|---|---|---|
| committer | Sagar Ghuge <sagar.ghuge@intel.com> | 2019-10-21 20:32:43 -0700 |
| commit | 18b28b5654e23c074e5158b2ce35c691733d7262 (patch) | |
| tree | 12bca86ac152eefe534c6be77762f46dc2e37853 | |
| parent | bf943bdf24be0e663aa866e26f06f9fddcbef155 (diff) | |
| download | mesa-18b28b5654e23c074e5158b2ce35c691733d7262.tar.gz | |
intel/compiler: Don't move immediate in register
On Gen12, we support mixed mode HF/F operands, and also 3 source
instruction supports immediate value support, so keep immediate as it
is, if it fits properly in 16 bit field.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
| -rw-r--r-- | src/intel/compiler/brw_fs_combine_constants.cpp | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_combine_constants.cpp b/src/intel/compiler/brw_fs_combine_constants.cpp index 182c24b5558..2a28351beef 100644 --- a/src/intel/compiler/brw_fs_combine_constants.cpp +++ b/src/intel/compiler/brw_fs_combine_constants.cpp @@ -313,6 +313,36 @@ needs_negate(const fs_reg *reg, const struct imm *imm) }; } +static bool +representable_as_hf(float f, uint16_t *hf) +{ + union fi u; + uint16_t h = _mesa_float_to_half(f); + u.f = _mesa_half_to_float(h); + + if (u.f == f) { + *hf = h; + return true; + } + + return false; +} + +static bool +represent_src_as_imm(const struct gen_device_info *devinfo, + fs_reg *src) +{ + /* TODO : consider specific platforms also */ + if (devinfo->gen == 12) { + uint16_t hf; + if (representable_as_hf(src->f, &hf)) { + *src = retype(brw_imm_uw(hf), BRW_REGISTER_TYPE_HF); + return true; + } + } + return false; +} + bool fs_visitor::opt_combine_constants() { @@ -336,10 +366,18 @@ fs_visitor::opt_combine_constants() if (!could_coissue(devinfo, inst) && !must_promote_imm(devinfo, inst)) continue; + bool represented_as_imm = false; for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file != IMM) continue; + if (!represented_as_imm && i == 0 && + inst->opcode == BRW_OPCODE_MAD && + represent_src_as_imm(devinfo, &inst->src[i])) { + represented_as_imm = true; + continue; + } + char data[8]; brw_reg_type type; if (!get_constant_value(devinfo, inst, i, data, &type)) |