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| author | Jason Ekstrand <jason@jlekstrand.net> | 2020-01-22 22:37:10 -0600 |
|---|---|---|
| committer | Dylan Baker <dylan@pnwbakers.com> | 2020-02-03 08:31:30 -0800 |
| commit | 23f23f23cbcfbd7f1e9dfbf81424ee0cbb5e058b (patch) | |
| tree | db367ef72c3a99aa87a4e46105a2fe707f465907 | |
| parent | d6868058763c4bbbf5ade6cb878f4e39445ac63a (diff) | |
| download | mesa-23f23f23cbcfbd7f1e9dfbf81424ee0cbb5e058b.tar.gz | |
anv: Improve BTI change cache flushing
This commit makes two changes:
1. We set pending_pipe_bits instead of emitting PIPE_CONTROL directly
for the flush at the end of cmd_buffer_begin_subpass.
2. Because BLORP ops such as vkCmdClearAttachments may come in the
middle of a render pass, we have to also flag the need for a cache
flush after the blorp op.
Fixes: 185630c6bc97 "anv/blorp: Do the gen11 BTI flush"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
(cherry picked from commit c70a786c77370bbc47f71a9f529d50116fd511da)
Conflicts:
src/intel/vulkan/genX_cmd_buffer.c
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_blorp_exec.c | 14 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 14 |
3 files changed, 29 insertions, 1 deletions
diff --git a/.pick_status.json b/.pick_status.json index 082452dfa95..ff19929c684 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1624,7 +1624,7 @@ "description": "anv: Improve BTI change cache flushing", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "185630c6bc973e9a2fec6172325bf31d70bc2eec" }, diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index 9c754f7318e..63476314937 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -268,6 +268,20 @@ genX(blorp_exec)(struct blorp_batch *batch, blorp_exec(batch, params); +#if GEN_GEN >= 11 + /* The PIPE_CONTROL command description says: + * + * "Whenever a Binding Table Index (BTI) used by a Render Taget Message + * points to a different RENDER_SURFACE_STATE, SW must issue a Render + * Target Cache Flush by enabling this bit. When render target flush + * is set due to new association of BTI, PS Scoreboard Stall bit must + * be set in this packet." + */ + cmd_buffer->state.pending_pipe_bits |= + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_STALL_AT_SCOREBOARD_BIT; +#endif + cmd_buffer->state.gfx.vb_dirty = ~0; cmd_buffer->state.gfx.dirty = ~0; cmd_buffer->state.push_constants_dirty = ~0; diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 9253b7e774b..8b2592282a2 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -4548,6 +4548,20 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, } cmd_buffer_emit_depth_stencil(cmd_buffer); + +#if GEN_GEN >= 11 + /* The PIPE_CONTROL command description says: + * + * "Whenever a Binding Table Index (BTI) used by a Render Taget Message + * points to a different RENDER_SURFACE_STATE, SW must issue a Render + * Target Cache Flush by enabling this bit. When render target flush + * is set due to new association of BTI, PS Scoreboard Stall bit must + * be set in this packet." + */ + cmd_buffer->state.pending_pipe_bits |= + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_STALL_AT_SCOREBOARD_BIT; +#endif } static enum blorp_filter |