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| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2019-01-17 09:33:39 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2019-01-23 11:31:14 +0100 |
| commit | 963c044c551b44aeab04984ef86634bcb10bacd7 (patch) | |
| tree | 805dbb6e25d87c909fc4f20dfeeff3627cd511dc | |
| parent | 5f0b17d5818163d6f46144071ebd5544fc341bc0 (diff) | |
| download | mesa-963c044c551b44aeab04984ef86634bcb10bacd7.tar.gz | |
radv: always pass the GFX9 fence data to si_cs_emit_cache_flush()
Remove two useless checks.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 11 | ||||
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 9 |
2 files changed, 4 insertions, 16 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index e75080d0975..2b17fbb339c 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -488,23 +488,16 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flush_bits flags) { if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) { - uint32_t *ptr = NULL; - uint64_t va = 0; - assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH)); - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { - va = cmd_buffer->gfx9_fence_va; - ptr = &cmd_buffer->gfx9_fence_idx; - } - radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4); /* Force wait for graphics or compute engines to be idle. */ si_cs_emit_cache_flush(cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.chip_class, - ptr, va, + &cmd_buffer->gfx9_fence_idx, + cmd_buffer->gfx9_fence_va, radv_cmd_buffer_uses_mec(cmd_buffer), flags, cmd_buffer->gfx9_eop_bug_va); } diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index f05096fcdfe..80093ed89ed 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -973,15 +973,10 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class; radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128); - uint32_t *ptr = NULL; - uint64_t va = 0; - if (chip_class == GFX9) { - va = cmd_buffer->gfx9_fence_va; - ptr = &cmd_buffer->gfx9_fence_idx; - } si_cs_emit_cache_flush(cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.chip_class, - ptr, va, + &cmd_buffer->gfx9_fence_idx, + cmd_buffer->gfx9_fence_va, radv_cmd_buffer_uses_mec(cmd_buffer), cmd_buffer->state.flush_bits, cmd_buffer->gfx9_eop_bug_va); |