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| author | Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> | 2019-07-19 10:34:53 -0700 |
|---|---|---|
| committer | Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> | 2019-07-22 09:33:48 -0700 |
| commit | 0345aeeb4015e824574ceca4f47ade512963c215 (patch) | |
| tree | 702ed019faf2d425cd83594be5443e17f55de09f | |
| parent | d07c846546ea1d75fad8f295ad11ae1a14311732 (diff) | |
| download | mesa-0345aeeb4015e824574ceca4f47ade512963c215.tar.gz | |
intel/compiler: Use nir_opt_conditional_discard
anv vkpipeline-db results for SKL:
total instructions in shared programs: 3622461 -> 3611281 (-0.31%)
instructions in affected programs: 396452 -> 385272 (-2.82%)
helped: 2062
HURT: 1
total cycles in shared programs: 1458144669 -> 1458105320 (<.01%)
cycles in affected programs: 4171830 -> 4132481 (-0.94%)
helped: 1874
HURT: 180
total loops in shared programs: 2437 -> 2437 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total spills in shared programs: 8745 -> 8748 (0.03%)
spills in affected programs: 8 -> 11 (37.50%)
helped: 1
HURT: 1
total fills in shared programs: 23392 -> 23395 (0.01%)
fills in affected programs: 8 -> 11 (37.50%)
helped: 1
HURT: 1
LOST: 0
GAINED: 1
No changes to shader-db on i965 or iris. The glsl compiler already
does a similar optimization.
Improvement suggested by Daniel Schürmann.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
| -rw-r--r-- | src/intel/compiler/brw_nir.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 675fe026695..ae81c65b94a 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -580,6 +580,7 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler, OPT(nir_opt_dce); } OPT(nir_opt_if, false); + OPT(nir_opt_conditional_discard); if (nir->options->max_unroll_iterations != 0) { OPT(nir_opt_loop_unroll, indirect_mask); } |