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| author | Ian Romanick <ian.d.romanick@intel.com> | 2022-11-08 13:53:25 -0800 |
|---|---|---|
| committer | Eric Engestrom <eric@engestrom.ch> | 2022-12-14 20:56:54 +0000 |
| commit | c1fad08d69661d0831eff0f3733c31ead33664ea (patch) | |
| tree | 41c1621eb8d11acac228314246c171087e8e1a40 | |
| parent | ae1fa524c4c427b70378a5d4918caf8137f48904 (diff) | |
| download | mesa-c1fad08d69661d0831eff0f3733c31ead33664ea.tar.gz | |
glsl_to_nir: Fix NIR bit-size of ir_triop_bitfield_extract and ir_quadop_bitfield_insert
Previously these would return result->bit_size of 32 even though the
type might have been int16_t or uint16_t. This prevents many assertion
failures in "glsl: Use nir_type_convert instead of
nir_type_conversion_op" on zink.
Fixes: 5e922fbc160 ("glsl_to_nir: fix bitfield_extract with 16-bit operands")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15121>
(cherry picked from commit 43da8223121b8807d2dd7fcf1276d145242365e6)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/compiler/glsl/glsl_to_nir.cpp | 19 |
2 files changed, 20 insertions, 1 deletions
diff --git a/.pick_status.json b/.pick_status.json index 11d3329733a..e5408be84e8 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -148,7 +148,7 @@ "description": "glsl_to_nir: Fix NIR bit-size of ir_triop_bitfield_extract and ir_quadop_bitfield_insert", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "5e922fbc160bcda9b38ccf5704cbd7276a748094" }, diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 4eb4fdf081d..27922743f3c 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/glsl/glsl_to_nir.cpp @@ -2361,11 +2361,25 @@ nir_visitor::visit(ir_expression *ir) result = ir->type->is_int_16_32() ? nir_ibitfield_extract(&b, nir_i2i32(&b, srcs[0]), nir_i2i32(&b, srcs[1]), nir_i2i32(&b, srcs[2])) : nir_ubitfield_extract(&b, nir_u2u32(&b, srcs[0]), nir_i2i32(&b, srcs[1]), nir_i2i32(&b, srcs[2])); + + if (ir->type->base_type == GLSL_TYPE_INT16) { + result = nir_i2i16(&b, result); + } else if (ir->type->base_type == GLSL_TYPE_UINT16) { + result = nir_u2u16(&b, result); + } + break; case ir_quadop_bitfield_insert: result = nir_bitfield_insert(&b, nir_u2u32(&b, srcs[0]), nir_u2u32(&b, srcs[1]), nir_i2i32(&b, srcs[2]), nir_i2i32(&b, srcs[3])); + + if (ir->type->base_type == GLSL_TYPE_INT16) { + result = nir_i2i16(&b, result); + } else if (ir->type->base_type == GLSL_TYPE_UINT16) { + result = nir_u2u16(&b, result); + } + break; case ir_quadop_vector: result = nir_vec(&b, srcs, ir->type->vector_elements); @@ -2374,6 +2388,11 @@ nir_visitor::visit(ir_expression *ir) default: unreachable("not reached"); } + + /* The bit-size of the NIR SSA value must match the bit-size of the + * original GLSL IR expression. + */ + assert(result->bit_size == glsl_base_type_get_bit_size(ir->type->base_type)); } void |