diff options
| author | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2022-12-05 20:27:59 +0200 |
|---|---|---|
| committer | Eric Engestrom <eric@engestrom.ch> | 2022-12-14 20:47:01 +0000 |
| commit | 7b5ba2d3639c6eb79a48645d6a2b9f311b552a86 (patch) | |
| tree | f0d3b2e7d9467a950527e61bdcf19079a7a95283 | |
| parent | e2fc0b33cdf3bb491e019e07f4b5c3880180628e (diff) | |
| download | mesa-7b5ba2d3639c6eb79a48645d6a2b9f311b552a86.tar.gz | |
intel: add missing restriction on fragment simd dispatch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7755
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20169>
(cherry picked from commit d4cd33630a9b90b95390f10d3aaa52f6f5e20245)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_compiler.h | 8 |
2 files changed, 9 insertions, 1 deletions
diff --git a/.pick_status.json b/.pick_status.json index 6020112696c..bed66e0841c 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -3604,7 +3604,7 @@ "description": "intel: add missing restriction on fragment simd dispatch", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 06d0c4d26ea..938845895ee 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -999,6 +999,14 @@ brw_fs_get_dispatch_enables(const struct intel_device_info *devinfo, *enable_32 = prog_data->dispatch_32; if (prog_data->persample_dispatch) { + /* TGL PRMs, Volume 2d: Command Reference: Structures: + * 3DSTATE_PS_BODY::32 Pixel Dispatch Enable: + * + * "Must not be enabled when dispatch rate is sample AND NUM_MULTISAMPLES > 1." + */ + if (devinfo->ver >= 12 && rasterization_samples > 1) + *enable_32 = false; + /* Starting with SandyBridge (where we first get MSAA), the different * pixel dispatch combinations are grouped into classifications A * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware |