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| author | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2021-10-26 14:27:18 +0300 |
|---|---|---|
| committer | Eric Engestrom <eric@engestrom.ch> | 2021-10-27 19:58:10 +0100 |
| commit | a82babccd1149576dc4332fbf60ea733b913b7b8 (patch) | |
| tree | b9efa2781ee8f57b5f5e965daa7305a65f07f003 | |
| parent | e4dc69796e68110a86494bc7360401c9806c19fa (diff) | |
| download | mesa-a82babccd1149576dc4332fbf60ea733b913b7b8.tar.gz | |
anv: fix push constant lowering with bindless shaders
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9fa1cdfe7ffd ("intel/rt: Implement push constants as global memory reads")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13529>
(cherry picked from commit a6031cd9bd409c793c3a2928eaf9f04f09d2f55a)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/intel/vulkan/anv_nir_compute_push_layout.c | 13 |
2 files changed, 12 insertions, 3 deletions
diff --git a/.pick_status.json b/.pick_status.json index d6ebfb10ef5..7c11aad287b 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -328,7 +328,7 @@ "description": "anv: fix push constant lowering with bindless shaders", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "9fa1cdfe7ffd9e7ebd83055e2008f3e4b8ada549" }, diff --git a/src/intel/vulkan/anv_nir_compute_push_layout.c b/src/intel/vulkan/anv_nir_compute_push_layout.c index 526e1a48f0b..66b8cd029c1 100644 --- a/src/intel/vulkan/anv_nir_compute_push_layout.c +++ b/src/intel/vulkan/anv_nir_compute_push_layout.c @@ -149,12 +149,21 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice, nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); switch (intrin->intrinsic) { - case nir_intrinsic_load_push_constant: + case nir_intrinsic_load_push_constant: { + /* With bindless shaders we load uniforms with SEND + * messages. All the push constants are located after the + * RT_DISPATCH_GLOBALS. We just need to add the offset to + * the address right after RT_DISPATCH_GLOBALS (see + * brw_nir_lower_rt_intrinsics.c). + */ + unsigned base_offset = + brw_shader_stage_is_bindless(nir->info.stage) ? 0 : push_start; intrin->intrinsic = nir_intrinsic_load_uniform; nir_intrinsic_set_base(intrin, nir_intrinsic_base(intrin) - - push_start); + base_offset); break; + } case nir_intrinsic_load_desc_set_address_intel: { b->cursor = nir_before_instr(&intrin->instr); |