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| author | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2021-03-17 21:30:52 +0200 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2021-03-19 13:51:02 -0700 |
| commit | 6041e3b07a891fe89c3b2081ce212022f0d40d33 (patch) | |
| tree | a8887ab6d5c887a3e6450aaad29f0f7d1b1ee96e | |
| parent | 85fafc91d2f7d35b545b1c0b23e4723e826ee51f (diff) | |
| download | mesa-6041e3b07a891fe89c3b2081ce212022f0d40d33.tar.gz | |
intel/fs/vec4: add missing dependency in write-on-write fixed GRFs
If we load constant data using pull constant SENDS, and we later load
that register with some other data, we can end up in a situation where
we don't track the initial fixed register write and therefore end up
using uninitialized registers.
This tracks write-on-write of fixed GRFs like we do for normal virtual
GRFs.
v2: Fix post_alloc_reg case (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9667>
(cherry picked from commit 8b6d22109f452b05ab1ce2028f7e18e50edcf325)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_schedule_instructions.cpp | 6 |
2 files changed, 6 insertions, 2 deletions
diff --git a/.pick_status.json b/.pick_status.json index 7755dcad87e..88623d93c96 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -985,7 +985,7 @@ "description": "intel/fs/vec4: add missing dependency in write-on-write fixed GRFs", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": null }, diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index d9f6f9d852f..d7c2230e8e1 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -1188,9 +1188,12 @@ fs_instruction_scheduler::calculate_deps() } } else if (inst->dst.file == FIXED_GRF) { if (post_reg_alloc) { - for (unsigned r = 0; r < regs_written(inst); r++) + for (unsigned r = 0; r < regs_written(inst); r++) { + add_dep(last_grf_write[inst->dst.nr + r], n); last_grf_write[inst->dst.nr + r] = n; + } } else { + add_dep(last_fixed_grf_write, n); last_fixed_grf_write = n; } } else if (inst->dst.is_accumulator()) { @@ -1418,6 +1421,7 @@ vec4_instruction_scheduler::calculate_deps() add_dep(last_mrf_write[inst->dst.nr], n); last_mrf_write[inst->dst.nr] = n; } else if (inst->dst.file == FIXED_GRF) { + add_dep(last_fixed_grf_write, n); last_fixed_grf_write = n; } else if (inst->dst.is_accumulator()) { add_dep(last_accumulator_write, n); |