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| author | Ian Romanick <ian.d.romanick@intel.com> | 2019-02-27 15:53:55 -0800 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2019-03-14 19:03:56 +0000 |
| commit | b638eb5db420fcc489abb652f147cf7390605325 (patch) | |
| tree | 84d843270398efcd994c5c2e502eee0f02dcba44 | |
| parent | 8448ece46090c1b387640b244959f1d45b23a764 (diff) | |
| download | mesa-b638eb5db420fcc489abb652f147cf7390605325.tar.gz | |
intel/fs: Fix extract_u8 of an odd byte from a 64-bit integer
In the old code, we would generate the exact same instruction for
extract_u8(some_u64, 0) and extract_u8(some_u64, 1). The mask-a-word
trick only works for even numbered bytes.
This fixes the (new) piglit test
tests/spec/arb_gpu_shader_int64/execution/fs-ushr-and-mask.shader_test.
v2: Use a SHR instead of an AND. This saves an instruction compared to
using two moves. Suggested by Jason.
Fixes: 6ac2d169019 ("i965/fs: Fix extract_i8/u8 to a 64-bit destination")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 55e6454d5e9dae6f8f29992af83f99217446da38)
[Emil: byte -> byte->u32[0] ]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5ea2a791eea..5d309a5a1b2 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1531,6 +1531,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W); bld.MOV(w_temp, subscript(op[0], type, byte->u32[0])); bld.MOV(result, w_temp); + } else if (byte->u32[0] & 1) { + /* Extract the high byte from the word containing the desired byte + * offset. + */ + bld.SHR(result, + subscript(op[0], BRW_REGISTER_TYPE_UW, byte->u32[0] / 2), + brw_imm_uw(8)); } else { /* Otherwise use an AND with 0xff and a word type */ bld.AND(result, |